Hybrid ASIC Verification Engineer (AI Silicon)

Cisco Systems, Inc; Capital; Híbrido; COP 223 964 000 - 303 951 000; Tempo integral

Resumo da oferta

Cisco Systems, Inc. is hiring a hybrid ASIC verification engineer based in Yerevan. The role focuses on test planning, testbench development, and collaboration across design and verification teams to ensure robust ASIC delivery.

You will work four days per week on-site at the Yerevan office and one day remotely, applying System Verilog, DVE/Verdi, and scripting skills to improve verification coverage and debugging efficiency.

Qualificações

• Bachelor’s or Master’s Degree in Electrical or Computer Engineering or related field.
• 1+ years of experience in design verification.
• Experience in test planning based on complex design specifications.
• Proven expertise in testbench development using System Verilog.
• Hands-on debugging experience with DVE and Verdi tools.
• Proficiency in scripting languages with Tcl, Python, or Perl.

Responsabilidades

• Drive comprehensive test planning and development of robust test benches.
• Collaborate with design, verification, and physical design teams to validate test logic.
• Identify and resolve technical issues using debugging tools and scripting.
• Develop verification strategies to ensure optimal coverage and efficiency.
• Deliver high-quality, reliable products that advance technology and innovation.

Conhecimentos

Test planning

SystemVerilog

Debugging

Scripting

DVE/Verdi

Testbench

Formação académica

Bachelor’s or Master’s Degree in Electrical or Computer Engineering

Ferramentas

DVE

Verdi

Descrição da oferta de emprego

Cisco Systems, Inc. is hiring a hybrid ASIC verification engineer based in Yerevan. The role focuses on test planning, testbench development, and collaboration across design and verification teams to ensure robust ASIC delivery.

You will work four days per week on-site at the Yerevan office and one day remotely, applying System Verilog, DVE/Verdi, and scripting skills to improve verification coverage and debugging efficiency.