Memory Layout Engineer - SRAM & Physical Design Expert

Cisco Systems, Inc; Capital; Hybrid; COP 287,954,000 - 479,923,000; Full time

Job summary

Cisco Systems, Inc. is seeking a senior-level physical design engineer for a hybrid role in Yerevan. You will implement SRAM layout and collaborate with international circuit teams to translate schematics into robust physical designs for critical silicon components.

The role requires 5+ years in physical design, experience with Cadence or Synopsys, and familiarity with nodes from 22nm down to 2nm. You will ensure DRC cleanliness and support tapeouts in a fast-paced, global team environment.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
• 5+ years of total professional experience in physical design or layout.
• Proven experience with Cadence or Synopsys EDA tools.
• Experience with advanced node technologies (TSMC 22nm to 2nm).

Responsibilities

• Implement high-quality memory layout focusing on SRAM blocks.
• Collaborate with international circuit design teams to translate schematics into physical designs.
• Perform post-layout simulations and apply corrections for DRC cleanliness and integration.
• Optimize layout designs for quality, visibility, and delivery speed of silicon components.

Skills

SRAM layout

EDA tools

English proficiency

Scripting (Tcl/Python)

Education

Bachelor's or Master's in Electrical/Computer Engineering

Tools

Cadence

Synopsys

Job description

Cisco Systems, Inc. is seeking a senior-level physical design engineer for a hybrid role in Yerevan. You will implement SRAM layout and collaborate with international circuit teams to translate schematics into robust physical designs for critical silicon components.

The role requires 5+ years in physical design, experience with Cadence or Synopsys, and familiarity with nodes from 22nm down to 2nm. You will ensure DRC cleanliness and support tapeouts in a fast-paced, global team environment.