Remote Hardware Verification Engineer: SoC & SystemVerilog

BairesDev; Colombia; Presencial; COP 190.834.000 - 286.250.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

100% remote

USD or local currency pay

Home workspace setup

Flexible hours

Paid parental leave

Mentorship & growth

Multicultural environment

Descripción de la vacante

At BairesDev, a global technology leader with 15+ years in delivering cutting-edge solutions, we seek a Hardware Verification Engineer to ensure digital chip designs align with specifications before fabrication. You will act as a quality gatekeeper in the hardware lifecycle, creating advanced environments to rigorously test complex logic.

You will develop verification plans, build scalable testbenches with SystemVerilog and UVM, and apply formal properties to detect pre-silicon defects.

Formación

• 4+ years of hardware verification or related fields.
• Verifying complex chip designs with SystemVerilog and UVM.
• Develop comprehensive testbenches and coverage models.
• Apply formal verification techniques to detect pre-silicon issues.
• Understand HDL and silicon fabrication lifecycles.
• Strong English communication.

Responsabilidades

• Develop verification plans and strategies for IP and SoC designs.
• Build and optimize scalable testbenches using SystemVerilog and UVM.
• Write and execute formal properties and assertions to catch defects early.
• Define functional coverage models and analyze results for sign-off.
• Collaborate with RTL designers to troubleshoot failures and refine architectures.

Conocimientos

SystemVerilog

UVM

Testbenches

Formal Verification

HDL Knowledge

English

Descripción del empleo

At BairesDev, a global technology leader with 15+ years in delivering cutting-edge solutions, we seek a Hardware Verification Engineer to ensure digital chip designs align with specifications before fabrication. You will act as a quality gatekeeper in the hardware lifecycle, creating advanced environments to rigorously test complex logic.

You will develop verification plans, build scalable testbenches with SystemVerilog and UVM, and apply formal properties to detect pre-silicon defects.