Remote RTL Design Engineer - ASIC & Verilog Expert

BairesDev; Colombia; Presencial; COP 349.862.000 - 540.695.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Remote work

USD or local currency

Home office setup provided

Flexible hours

Paid parental leave

Mentorship & growth opportunities

Global collaboration

Descripción de la vacante

BairesDev is seeking a seasoned RTL Design Engineer to shape the register-transfer level logic for ASIC chips. You will translate architectures into high‑quality digital designs with Verilog and SystemVerilog, contributing across the full design flow from synthesis to fabrication.

Join a 100% remote team delivering world‑class solutions, with flexible hours and strong growth opportunities, working with the global Top 1% of talent.

Formación

• 4+ years of experience in RTL/Digital/ASIC design.
• Expertise in RTL design for ASIC chips.
• Proficiency in Verilog and SystemVerilog.
• Experience with ASIC design, synthesis, and digital architecture.
• Advanced English proficiency.

Responsabilidades

• Design and develop RTL logic modules for ASICs using Verilog/SystemVerilog.
• Translate architectural requirements into robust digital designs for ASIC implementation.
• Perform logic synthesis and optimize for power, performance, and area.
• Collaborate with cross-functional teams to validate design correctness.
• Manage the architecture through the full design flow toward fabrication.

Conocimientos

RTL design

Verilog

SystemVerilog

ASIC design

Digital architecture

English (Advanced)

Descripción del empleo

BairesDev is seeking a seasoned RTL Design Engineer to shape the register-transfer level logic for ASIC chips. You will translate architectures into high‑quality digital designs with Verilog and SystemVerilog, contributing across the full design flow from synthesis to fabrication.

Join a 100% remote team delivering world‑class solutions, with flexible hours and strong growth opportunities, working with the global Top 1% of talent.