Senior Digital RTL Design & Verification Architect

Ignite Next GmbH; Zürich; Hybrid; CHF 160.000 - 230.000; Vollzeit

Zusammenfassung

Ignite Next GmbH in Zürich, Switzerland seeks a senior digital design/verification engineer to own parts of our compute-in-memory IP portfolio, delivering clean SystemVerilog RTL and UVM environments.

You will implement memory-mapped controls, AXI bridges, DMA and datapaths, optimize power, develop constrained-random tests, run GLS/CDC checks, and produce reusable components, regression suites, and clear documentation for tape-out readiness.

Qualifikationen

• 5+ years in digital design or verification for ASIC
• Hands-on experience with either RISC-V or ARM architectures
• Knowledge of synthesis basics and how RTL choices impact timing/power/area
• Clear technical communication and ability to create reusable components

Aufgaben

• Implement RTL: memory-mapped blocks, bridges, FIFOs, arbiters, DMA, datapaths; write synthesis-friendly code with reset/CDC strategy
• Extreme optimization for power with a power-driven mindset
• Develop UVM testbenches (agents, sequencers, scoreboards); drive constrained-random and directed testing; close coverage

Kenntnisse

SystemVerilog RTL

UVM

RISC-V/ARM familiarity

Synthesis basics

Technical communication

Jobbeschreibung

Ignite Next GmbH in Zürich, Switzerland seeks a senior digital design/verification engineer to own parts of our compute-in-memory IP portfolio, delivering clean SystemVerilog RTL and UVM environments.

You will implement memory-mapped controls, AXI bridges, DMA and datapaths, optimize power, develop constrained-random tests, run GLS/CDC checks, and produce reusable components, regression suites, and clear documentation for tape-out readiness.