Senior Custom SRAM & Compute-in-Memory Design Lead

Ignite Next GmbH; Zürich; Hybrid; CHF 180.000 - 240.000; Vollzeit

Zusammenfassung

Ignite Next GmbH in Zürich, Switzerland invites a senior hardware architect to lead development of compute-in-memory SRAM (ComputeRAM). You will own architecture, circuit design, verification, and silicon correlation for 5 nm and below, and manage a small team of custom designers and layout engineers.

The role focuses on bitcell-adjacent periphery, datapath interfaces, data movement optimization, and close collaboration with layout, digital, backend, DFT, and test to deliver production-grade

Qualifikationen

• 7+ years in custom digital, memory, or analog design.
• End-to-end ownership of production-grade functional blocks, including sign-off and silicon correlation.
• Strong collaboration with layout, digital, backend, DFT and test teams.
• Experience with high-performance, low-power design on advanced nodes (FinFET, 5 nm+).

Aufgaben

• Own the product roadmap: define specs, PPA targets, verification depth, and quality bars for new SRAM variants and adjacent blocks.
• Design and verify memory or datapath subsystems (sense amps, data drivers, multipliers, adders, register files, timing/control FSMs).
• Architect for advanced nodes: manage variation, stability, noise, wake-up and low-power behavior.
• Define clean digital boundaries and timing budgets for integration into mixed-signal flows.
• Plan bring-up, build characterization benches, analyze ATE data, publish correlation/errata with fixes.
• Specify and validate redundancy/repair schemes; coordinate with MBIST/Scan test coverage.
• Collaborate with layout on floorplans, matching, shielding, routing; address EM/IR early.
• Mentor designers, run reviews, enforce checklists, and grow automation (Python/Tcl).

Kenntnisse

Team leadership

Memory design

Digital design

Verification

Python scripting

Ausbildung

MS or PhD in Electrical/Computer Engineering

Tools

Python

Tcl

DFT tools

Jobbeschreibung

Ignite Next GmbH in Zürich, Switzerland invites a senior hardware architect to lead development of compute-in-memory SRAM (ComputeRAM). You will own architecture, circuit design, verification, and silicon correlation for 5 nm and below, and manage a small team of custom designers and layout engineers.

The role focuses on bitcell-adjacent periphery, datapath interfaces, data movement optimization, and close collaboration with layout, digital, backend, DFT, and test to deliver production-grade