Standard Custom Design Engineer

Ignite Next GmbH; Zürich; Hybrid; CHF 140.000 - 190.000; Vollzeit

Zusammenfassung

Ignite Next GmbH in Zürich, Switzerland, seeks a senior mixed-signal IC designer (MS +4 years or PhD) to drive design, verification, and characterization of custom blocks and memories for ComputeRAM technology.

You will collaborate with digital and layout teams to meet aggressive PPA targets on advanced CMOS nodes, down to 4nm and below, tackling multi-disciplinary timing constraints and IP-quality deliverables.

Qualifikationen

• Hands-on sub-28 nm CMOS experience.
• Quality-oriented approach.
• Proven design ownership in datapath/standard cells, memory/SRAM, data-converters, ultra-low-power, PLLs, or sensor signal chains.
• Clear technical communication; structured planning; cross-functional collaboration with digital/custom/layout.

Aufgaben

• Design & verify mixed-signal circuits/subsystems for ASICs (architecture, transistor-level design, sim, corners/Monte-Carlo, modelling).
• Develop AI-related building blocks as part of our in-memory computing technology.
• Partner across disciplines on interfaces, buses/standard-cell boundaries, and timing/power budgets.
• Contribute to IP-quality specifications, reviews, reusable verification collateral, and documentation for internal reuse and customer delivery.
• Continuously improve flows through scripting/automation (e.g., Python/Tcl) for characterization, report generation, and regressions.

Kenntnisse

Mixed-signal design

Datapath design

Memory/SRAM design

CMOS process 28nm+

Verilog/VHDL

Python scripting

Digital-analog interfaces

Power/Timing analysis

Ausbildung

PhD in Electrical Engineering

MSc in Electrical Engineering

Tools

Cadence Virtuoso

SPICE simulators

Python

Verilog/VHDL

Mentor Graphics

Jobbeschreibung

Zürich, Switzerland
Seniority: MS +4 years or PhD

Own critical mixed-signal subsystems that bring our compute-in-memory SRAM (ComputeRAM®) from design to silicon and into production. You will design, verify, and characterize custom blocks, including full-custom digital datapaths and memories, and collaborate tightly with our digital and layout teams to hit aggressive PPA and quality targets on modern CMOS nodes, down to 4nm and below. You will deal with multi-disciplinary topics ranging from traditional mixed-signal design to solving digital timing constraints.

What you’ll do

• Design & verify mixed-signal circuits/subsystems for ASICs (architecture, transistor-level design, simulation, corners/Monte-Carlo, modelling).
• Develop AI-related building blocks as part of our in-memory computing technology.
• Partner across disciplines on interfaces, buses/standard-cell boundaries, and timing/power budgets.
• Contribute to IP-quality specifications, reviews, reusable verification collateral, and documentation ready for internal reuse and customer delivery.
• Continuously improve flows through scripting/automation (e.g., Python/Tcl) for characterization, report generation, and regressions, guaranteeing reproducibility and reliability. (Nice-to-have but valued.)

Outcomes (first 18 months)

• Complete and document one or more IP blocks
• Tape-in and silicon of at least one sub-system meeting spec across PVT; complete post-production test plan and correlation report signed off.

Requirements

• Hands-on sub-28 nm CMOS experience
• Quality-oriented approach
• Proven design ownership in one or more of: datapath/standard cells design, memory/SRAM design, data-converters, ultra-low-power amps, power-management, references, PLLs, sensor signal processing chains.
• Clear technical communication; structured planning; comfort working cross-functionally with digital/custom/layout.

Nice to have

• Exposure to datapath/arith/bus/standard-cell co-design boundaries (device-level parasitics, signal-integrity hand-offs, and glitch reduction).
• Scripting for automation (Python/Tcl) in mixed-signal flows
• Familiarity with compute-in-memory or memory-periphery constraints (matching, IR/EM, variation, testability)

Interview flow (indicative)

1. 30-min intro with HR (role/context)
2. First Technical deep dive
3. Second Technical Deep Dive
4. (Optional) Third Technical Deep Dive
5. Systems/product conversation with management