Senior IC Layout Engineer - FinFET

IC Resources; Lausanne; Hybrid; CHF 120.000 - 160.000; Vollzeit

Benefits dieser Stelle

Pension

Private medical cover

Visa sponsorship

Relocation support

Zusammenfassung

IC Resources is seeking a Senior IC Layout Engineer for a growing semiconductor team in Lausanne. The role features a hybrid working model with three days per week in the office and a focus on custom analog layout and physical verification.

You will handle layout and verification for high-speed designs, including multi-gigabit SerDes and memory interfaces, and may take ownership of broader chip layout activities as you progress.

Qualifikationen

• Experience in analog IC layout and verification.
• Strong layout techniques for matching and parasitic reduction.
• Familiarity with high-speed/high-frequency designs (RF, SerDes) is a plus.

Aufgaben

• Develop custom analog layouts for circuits, blocks and IP.
• Work on high-speed/frequency circuits including amplifiers, PLLs, DLLs, oscillators, buffers, regulators and data converters.
• Apply layout techniques for matching, parasitic reduction, power distribution and ESD.
• Support full chip layout, integration and physical verification activities.
• Perform DRC, LVS, parasitic extraction, EM and IR drop analysis.
• Work with 28nm, 16nm and 7nm process technologies.
• Use Cadence Virtuoso, Calibre and PVS.

Kenntnisse

Analog IC Layout

High-speed circuit design

Layout optimization

Tools

Cadence Virtuoso

Calibre

PVS

Jobbeschreibung

I am exclusively recruiting for a Senior IC Layout Engineer to join my client's growing semiconductor team in Lausanne. The role offers hybrid working, with 3 days per week in the office.

The Senior IC Layout Engineer will be responsible for custom layout and physical verification of analog circuits, blocks and IP used in advanced high-speed semiconductor designs, including multi-gigabit SerDes and memory interfaces.

There is also scope to take ownership of wider chip layout activities and progress into a more senior technical position.

Key responsibilities:

• Develop custom analog layouts for circuits, blocks and IP
• Work on high-speed and high-frequency circuits including amplifiers, PLLs, DLLs, oscillators, buffers, regulators and data converters
• Apply layout techniques for matching, parasitic reduction, power distribution and ESD
• Support full chip layout, integration and physical verification activities
• Perform DRC, LVS, parasitic extraction, EM and IR drop analysis
• Work with advanced process technologies including 28nm, 16nm and 7nm
• Use industry standard tools such as Cadence Virtuoso, Calibre and PVS

My client is looking for an experienced Analog IC Layout Engineer. High speed experience would be advantageous, but is not essential if you have strong experience with complex analog or high-frequency designs.

The package includes a competitive salary, pension, private medical cover, visa sponsorship and relocation support where required.