Senior Analog IC Layout Engineer - Hybrid, High-Speed

IC Resources; Lausanne; Hybrid; CHF 120.000 - 160.000; Vollzeit

Benefits dieser Stelle

Pension

Private medical cover

Visa sponsorship

Relocation support

Zusammenfassung

IC Resources is seeking a Senior IC Layout Engineer for a growing semiconductor team in Lausanne. The role features a hybrid working model with three days per week in the office and a focus on custom analog layout and physical verification.

You will handle layout and verification for high-speed designs, including multi-gigabit SerDes and memory interfaces, and may take ownership of broader chip layout activities as you progress.

Qualifikationen

• Experience in analog IC layout and verification.
• Strong layout techniques for matching and parasitic reduction.
• Familiarity with high-speed/high-frequency designs (RF, SerDes) is a plus.

Aufgaben

• Develop custom analog layouts for circuits, blocks and IP.
• Work on high-speed/frequency circuits including amplifiers, PLLs, DLLs, oscillators, buffers, regulators and data converters.
• Apply layout techniques for matching, parasitic reduction, power distribution and ESD.
• Support full chip layout, integration and physical verification activities.
• Perform DRC, LVS, parasitic extraction, EM and IR drop analysis.
• Work with 28nm, 16nm and 7nm process technologies.
• Use Cadence Virtuoso, Calibre and PVS.

Kenntnisse

Analog IC Layout

High-speed circuit design

Layout optimization

Tools

Cadence Virtuoso

Calibre

PVS

Jobbeschreibung

IC Resources is seeking a Senior IC Layout Engineer for a growing semiconductor team in Lausanne. The role features a hybrid working model with three days per week in the office and a focus on custom analog layout and physical verification.

You will handle layout and verification for high-speed designs, including multi-gigabit SerDes and memory interfaces, and may take ownership of broader chip layout activities as you progress.