Advanced R&D - Analog Layout Engineer

Kandou AI; Saint-Sulpice; Vor Ort; CHF 120.000 - 160.000; Vollzeit

Zusammenfassung

Kandou AI in Lausanne, Switzerland, is seeking an experienced Advanced R&D Analog Layout Engineer to own the physical realization of high-speed mixed-signal front-ends.

You will work with analog designers to translate schematics into silicon-ready layouts that meet performance, matching, parasitic, EM/IR and ESD targets, and you will support post-silicon characterization.

Qualifikationen

• 5+ years of custom analog layout for high-speed SerDes, memory IO, or HF/RF circuits.
• Experience laying out analog blocks in FinFETs (28 nm–7 nm).
• Knowledge of matching constraints, parasitic minimization, power-grid and ESD for high-speed circuits.
• Proficient with Cadence Virtuoso, Spectre/HSPICE, Calibre/PVS, and parasitic extraction tools.

Aufgaben

• Own the end-to-end physical implementation of assigned analog blocks: floor-planning, placement, routing, power grid, ESD, DRC/LVS/PEX sign-off.
• Collaborate with analog designers to meet matching, parasitic, shielding constraints and iterate on post-layout performance.
• Support IP-level and chip-level integration with digital, packaging, and external customers.
• Verify performance across process/voltage/temperature corners and drive parasitic reduction.
• Support post-silicon bring-up, debugging, and characterization; feed observations into future revisions.
• Produce layout, verification, and progress reports; participate in design reviews.

Kenntnisse

Analog layout

High-speed design

FinFET knowledge

Layout optimization

Electronics analysis

Ausbildung

BSc/MSc in electronics/electrical engineering

Tools

Cadence Virtuoso

Spectre/HSPICE

Calibre/PVS

Jobbeschreibung

At Kandou, we are redefining the economics of AI infrastructure. Our mission is to democratise AI by significantly reducing the Total Cost of Ownership (TCO) of hardware systems — a critical barrier to scalable adoption.

Our proprietary MIMO-over-copper technology powers a high-performance, chiplet-based AI memory fabric that is both scalable and energy-efficient. Unlike traditional interconnects, our solution reduces power consumption significantly while preserving high bandwidth and ultra-low latency — unlocking unprecedented efficiency for AI training and inference at scale.

Job title: Advanced R&D - Analog Layout Engineer

Location : Lausanne, Switzerland

The Analog Layout Engineer owns the physical realization of the mixed-signal front-ends of our high-speed chip-to-chip and die-to-die link IPs in advanced FinFET nodes. You will work hand-in-hand with analog designers to convert schematics into silicon-ready layouts that meet aggressive performance, matching, parasitic, EM/IR, and ESD targets — and you will follow the block through post-silicon characterization to close the loop between what was drawn and what measures.

Immediate key objective

• Own the layout of one or more critical analog blocks (e.g., CTLE, PLL, ADC/DAC, LDO, high-speed I/O) and deliver DRC/LVS-clean, parasitic-verified layouts that meet block-level specification.

• Establish and enforce matching, floor-planning, shielding, and power-grid strategies for the next-generation link, in close collaboration with the analog design team.

• Support first-silicon bring-up and characterization, closing the loop between measured behavior and the parasitic / EM assumptions used at layout time.

Responsibility

• Own the end-to-end physical implementation of assigned analog blocks: floor-planning, device placement, routing, power grid, ESD strategy, and DRC/LVS/PEX sign-off.

• Partner with analog designers to interpret matching, parasitic, and shielding constraints, and to iterate quickly on post-layout performance.

• Support IP-level and chip-level integration, including interaction with digital, packaging, and IP-delivery teams and with external customers.

• Verify performance across process/voltage/temperature corners at post-layout, and drive parasitic reduction where needed to meet specification.

• Support post-silicon bring-up, debug, and characterization on lab equipment; feed measured parasitic and layout observations back into future revisions.

• Produce clear layout, verification, and progress reports; contribute to layout-level design reviews.

Required Experience

• 5+ years doing custom analog layout for multi-Gigabit SerDes transceivers (28 Gb/s and beyond), memory I/O, or HF/RF circuits.

• Hands-on experience laying out the fundamental analog building blocks in modern FinFET technologies (28 nm, 14/16 nm, 7 nm): amplifiers, oscillators, PLLs/DLLs, biasing, buffers, regulators, filters, and data converters.

• Working knowledge of matching constraints, parasitic minimization, power-grid design, and ESD requirements for high-speed circuits.

• Proficient with the modern analog layout tool chain (Cadence Virtuoso, Spectre/HSPICE, Calibre/PVS DRC/LVS, parasitic extraction, EM/IR-drop and ESD analysis tools).

• Awareness of power and thermal budgeting for high-speed IPs at reticle-scale packages.

• Experience with reliability, EM, and aging analysis in advanced nodes.

• Exposure to flip-chip package technologies and to package-aware floor-planning of the die.

• Prior tape-out and silicon characterization in FinFET technologies

Required Skills

• Deep understanding of high-speed, high-precision analog layout techniques, including matching, symmetry, shielding, and controlled- impedance routing.

• Proficient with Cadence Virtuoso, Spectre/HSPICE, Calibre/PVS DRC/LVS, parasitic extraction and modeling, EM/IR-drop and ESD analysis tools.

• Skilled in translating design intent (matching, parasitic budgets, shielding requirements) into concrete floor-plans and routing rules.

• Strong analytical and problem-solving skills.

• Self-motivated, with strong sense of ownership; comfortable managing workload against schedules and reporting to internal management and technical audiences.

Required Education

• MSc or BSc in electronics/electrical engineering (equivalent or higher), with a strong background in semiconductor physics.

https://kandou.ai/