Senior Digital Design Engineer – High‑Speed AI Hardware

Kandou AI; Saint-Sulpice; Vor Ort; CHF 90.000 - 120.000; Vollzeit

Zusammenfassung

Kandou is seeking a Digital Design Engineer in Lausanne (St-Sulpice), Switzerland. The role focuses on defining interfaces, RTL design, timing analysis, and IP verification for high-speed digital circuits in a cutting-edge AI infrastructure context.

You will collaborate with Verification and Analog/Mixed-signal teams, develop block-level specs, and support post-silicon bring-up, while working with Cadence tools and industry-standard design methodologies.

Qualifikationen

• 5-10 years’ experience in digital design of key circuits in multi-Gigabit serial data-link transceivers.
• Strong background in high-speed digital circuits using deep-submicron CMOS.
• Experience with EDA tools and verification methodologies.

Aufgaben

• Define analog to digital interface specifications.
• RTL design and IP verification basics.
• Synthesis and timing analysis.
• Collaborate with Verification and Analog/Mixed-signal teams.
• Develop block level specs for high-speed digital circuits.
• Design and verification of high-speed digital circuits.
• Support post-silicon lab bring-up and productization.
• Understand high-speed serial protocols (USB4, PCIe).
• Interface with analog/digital designers.
• Validate chips in lab and ensure compliance.
• Support IP and chip level integration.
• Manage workload and report to management/customers.

Kenntnisse

Digital design

RTL coding

Python scripting

High-speed IO

CMOS technologies

Verification

Ausbildung

MSc in EE

Tools

Cadence toolset

Simulation tools

Verification tools

Jobbeschreibung

Kandou is seeking a Digital Design Engineer in Lausanne (St-Sulpice), Switzerland. The role focuses on defining interfaces, RTL design, timing analysis, and IP verification for high-speed digital circuits in a cutting-edge AI infrastructure context.

You will collaborate with Verification and Analog/Mixed-signal teams, develop block-level specs, and support post-silicon bring-up, while working with Cadence tools and industry-standard design methodologies.