SerDes Architect: System-Level Modeling for AI Chips

Kandou Bus SA; Lausanne; Hybrid; CHF 110.000 - 150.000; Vollzeit

Zusammenfassung

Kandou seeks a SerDes Architecture and Modeling Engineer in Lausanne, Switzerland to advance system-level modelling of serial links using MATLAB, Python and C++. You will collaborate with architects to budget the link and define transceiver specs.

You will implement and document software, work with analog, digital and verification teams, and apply knowledge of control theory, signal processing and SPICE/SPECTRE simulations to ensure high-performance, low-latency links for AI hardware.

Qualifikationen

• Strong knowledge of control theory and digital algorithms.
• Experience implementing signal-processing algorithms.
• Understanding of digital communication link components and clock recovery concepts.
• Proficiency in C++, MATLAB, or Python/NumPy.
• Familiar with git version-control and software engineering basics (unit tests, profiling).
• Familiar with SPICE/SPECTRE analog circuit simulators.
• Familiar with signal integrity principles.
• Strong communication and presentation skills.

Aufgaben

• Implement, document, and maintain software for system-level modelling of serial communication links in MATLAB, Python, and C++.
• Work closely with system architects to budget the link and define block-level specs of the transceiver.
• Work closely with analog, digital, and verification teams in order to support the design and verification process.

Kenntnisse

Control theory

Signal processing

Digital algorithms

C++

Python

MATLAB

Git

SPICE/SPECTRE

Signal integrity

Communication systems

Presentation skills

Ausbildung

Bachelor of Engineering in Electronics and Electrical Engineering, Communications Systems, or Computer Science

Tools

MATLAB

Python

C++

NumPy

Git

SPICE/SPECTRE

Jobbeschreibung

Kandou seeks a SerDes Architecture and Modeling Engineer in Lausanne, Switzerland to advance system-level modelling of serial links using MATLAB, Python and C++. You will collaborate with architects to budget the link and define transceiver specs.

You will implement and document software, work with analog, digital and verification teams, and apply knowledge of control theory, signal processing and SPICE/SPECTRE simulations to ensure high-performance, low-latency links for AI hardware.