Advanced R&D Analog Design Engineer

Kandou Bus SA; Saint-Sulpice; Vor Ort; CHF 120.000 - 180.000; Vollzeit

Zusammenfassung

Kandou Bus SA in Switzerland is seeking an Advanced R&D Analog Design Engineer to push the limits of high‑speed, high‑precision circuits. You will design, simulate, and verify analog blocks and contribute to the chiplet‑based AI memory fabric roadmap.

You will collaborate with layout, design, and system teams, work on multi‑gigabit transceivers, PLLs, and biasing circuits, and help deliver silicon that improves performance and energy efficiency for AI workloads.

Qualifikationen

• 5+ years of experience in analog and mixed-signal circuit design and layout, with high-speed/high-precision emphasis.
• MSc or PhD in electronics or related field; experience with CMOS process nodes is preferred.
• Strong background in signal processing, simulations, and layout verification.

Aufgaben

• Develop block-level specifications and models for target designs.
• Design, model, and verify performance of analog circuits in advanced nodes.
• Layout design, floor-planning, and post-layout verification guidance.
• Perform design verification at pre- and post-layout stages with variation awareness.
• Collaborate with design, layout, and chip‑level teams; support post‑silicon bring‑up and characterization.
• Produce progress and technical reports; contribute to concept-level architectures.

Kenntnisse

Analog design

Layout techniques

High-speed circuits

Testbenches & simulations

Signal integrity

Communication & reporting

Ownership & responsibility

Ausbildung

MSc or PhD in electronics / electrical engineering

Bachelor’s degree in electronics / EE

Tools

Cadence Virtuoso

Spectre/HSpice

Calibre/PVS

DRC/LVS

Parasitic extraction and modelling

EM/IR drop tools

ESD analysis

Jobbeschreibung

Advanced R&D Analog Design Engineer

At Kandou, we are redefining the economics of AI infrastructure. Our mission is to democratize AI by significantly reducing the total cost of ownership of hardware systems, a critical barrier to scalable adoption.

Our proprietary MIMO‑over‑copper technology powers a high‑performance, chiplet‑based AI memory fabric that is both scalable and energy‑efficient. Unlike traditional interconnects, our solution reduces power consumption while preserving high bandwidth and ultra‑low latency—unlocking unprecedented efficiency for AI training and inference at scale.

Kandou’s architecture is not just an incremental improvement—it’s a foundational shift in how AI hardware is built for the future.

Key Responsibilities

• Develop block‑level specifications and models for target designs
• Design, model, and verify performance of custom analog circuits in advanced technology nodes
• Layout design and development, including floor‑planning, guiding layout engineers, and post‑layout verification
• Perform design verification at different levels (pre‑ and post‑layout, variation‑aware)
• Support and collaborate with design and layout engineers, architects, chip‑level integration engineers, modeling and system‑level designers
• Support post‑silicon lab bring‑up, debug, characterization, and productization
• Produce reports (progress, analysis, design, modeling, verification)
• Participate in developing concept‑level architectures and circuits

Required Skills

• Deep understanding of design and layout techniques for high‑speed and high‑precision circuits
• Experience developing testbenches and simulation setups for performance analysis of target circuits and systems
• Proficient in layout techniques such as matching, parasitic estimation and reduction, and deep‑submicron issues
• Advanced user of EDA tools for design and verification, preferably Cadence Virtuoso, Spectre/HSpice, Calibre/PVS, DRC/LVS, parasitic extraction and modelling, EM and IR drop tools, and ESD analysis
• Strong analytical, communication, and reporting skills
• Self‑motivated with a strong sense of ownership and responsibility
• Ability to manage workload, schedules, and report to internal management and technical teams

Experience & Qualifications

• 5+ years of experience in design and layout of analog and mixed‑signal circuits, especially high‑speed and high‑precision circuits (e.g., multi‑gigabit serial data‑link transceivers, RF circuits, equalizers, clock generators, PLLs, clock and data recovery circuits, data converters, biasing and bandgap circuits)
• MSc or PhD in electronics/ electrical engineering (or equivalent)
• Experience with modern semiconductor process technologies (CMOS 28 nm, FinFET 16/14 nm, 7 nm)
• Experience in high‑level modelling, top‑level simulations, signal integrity, and solid background in signal processing and communications

Location & Work Details

• Work location 1025 St‑Sulpice, VD (Innovation Park, EPFL)
• Workload 100%
• Employment start Immediately
• Employment duration Permanent

Qualifications & Work Experience

• Skilled
• More than 3 years
• Bachelor’s degree from a university or equivalent

Language Skills

• English – Very good knowledge (oral and written)
• French – Good knowledge (oral and written)