Senior Analog Design Engineer - High-Speed SerDes

Kandou AI; Saint-Sulpice; Vor Ort; CHF 90.000 - 140.000; Vollzeit

Zusammenfassung

Kandou AI in Europe is seeking an Analog Design Engineer to drive design, modeling and verification of high‑speed Serdes transceivers in advanced technology nodes. You will collaborate with architects, layout, verification and silicon teams to meet performance, power and reliability targets.

The role requires a Master’s or Ph.D. in Electronics and 5+ years of hands‑on analog design experience, including oscillators, PLLs and RF blocks, with Cadence Virtuoso and finFET process familiarity.

Qualifikationen

• Master’s or Ph.D. in Electronics or related field.
• Minimum 5 years of experience in analog design and layout of key circuits in high-speed transceivers.
• Expertise in design and layout of high-speed circuits (oscillators, PLLs, DLLs, etc.).
• Experience with finFET technologies and modern process nodes.
• Experience using Ocean/MDL or equivalents to automate analog design verification is desirable.

Aufgaben

• Position in design, modeling, and verification of analog designs for high-speed Serdes transceivers.
• Design and verification of analog circuits following design/documentation flows to meet specs.
• Interact with customers on requirements, design specs, performance results and delivery when needed.
• Support analog IP and chip-level integration.
• Collaborate with architects, leads, layout, verification and silicon teams as needed.

Kenntnisse

High-speed analog Serdes design

DFT/DFM/ESD protection

Layout techniques for high-speed CirCU

Ausbildung

Master’s or Ph.D. in Electronics

Tools

Cadence Virtuoso

Ocean/MDL automation

Jobbeschreibung

Kandou AI in Europe is seeking an Analog Design Engineer to drive design, modeling and verification of high‑speed Serdes transceivers in advanced technology nodes. You will collaborate with architects, layout, verification and silicon teams to meet performance, power and reliability targets.

The role requires a Master’s or Ph.D. in Electronics and 5+ years of hands‑on analog design experience, including oscillators, PLLs and RF blocks, with Cadence Virtuoso and finFET process familiarity.