Senior Analog Design Engineer – AI Hardware R&D

Kandou Bus SA; Saint-Sulpice; Vor Ort; CHF 120.000 - 180.000; Vollzeit

Zusammenfassung

Kandou Bus SA in Switzerland is seeking an Advanced R&D Analog Design Engineer to push the limits of high‑speed, high‑precision circuits. You will design, simulate, and verify analog blocks and contribute to the chiplet‑based AI memory fabric roadmap.

You will collaborate with layout, design, and system teams, work on multi‑gigabit transceivers, PLLs, and biasing circuits, and help deliver silicon that improves performance and energy efficiency for AI workloads.

Qualifikationen

• 5+ years of experience in analog and mixed-signal circuit design and layout, with high-speed/high-precision emphasis.
• MSc or PhD in electronics or related field; experience with CMOS process nodes is preferred.
• Strong background in signal processing, simulations, and layout verification.

Aufgaben

• Develop block-level specifications and models for target designs.
• Design, model, and verify performance of analog circuits in advanced nodes.
• Layout design, floor-planning, and post-layout verification guidance.
• Perform design verification at pre- and post-layout stages with variation awareness.
• Collaborate with design, layout, and chip‑level teams; support post‑silicon bring‑up and characterization.
• Produce progress and technical reports; contribute to concept-level architectures.

Kenntnisse

Analog design

Layout techniques

High-speed circuits

Testbenches & simulations

Signal integrity

Communication & reporting

Ownership & responsibility

Ausbildung

MSc or PhD in electronics / electrical engineering

Bachelor’s degree in electronics / EE

Tools

Cadence Virtuoso

Spectre/HSpice

Calibre/PVS

DRC/LVS

Parasitic extraction and modelling

EM/IR drop tools

ESD analysis

Jobbeschreibung

Kandou Bus SA in Switzerland is seeking an Advanced R&D Analog Design Engineer to push the limits of high‑speed, high‑precision circuits. You will design, simulate, and verify analog blocks and contribute to the chiplet‑based AI memory fabric roadmap.

You will collaborate with layout, design, and system teams, work on multi‑gigabit transceivers, PLLs, and biasing circuits, and help deliver silicon that improves performance and energy efficiency for AI workloads.