Senior Digital Design Engineer — High-Speed AI Memory Fabric

Kandou Bus SA; Schweiz; Remote; CHF 90,000 - 130,000; Full time

Job summary

Kandou Bus SA in Lausanne, Switzerland, seeks a Digital Design Engineer to define concepts, design RTL and verify high-speed digital circuits for its MIMO-over-copper platform. You will work with verification and analog/mixed-signal teams to ensure timing, power and area targets, while engaging with customers on specifications and results.

Applicants should have 5–10 years in digital design, experience with Cadence tools, and a Master’s or PhD in E.E.

Qualifications

• 5-10 years of digital design experience in multi-Gigabit serial data-link transceivers.
• Experience in DDR and modern memory interfaces is required.
• Strong background in high-speed digital circuit design in deep-submicron CMOS technologies.
• Proven track record in design and verification of data processing systems.
• Exposure to analog/digital interfaces and verification methodologies is advantageous.
• Experience with industry standard EDA tools for design, simulation and verification.

Responsibilities

• Concept definition and analog-to-digital interface specification.
• RTL design and basic DFT/IP verification.
• Logic synthesis and timing analysis.
• Collaborate with verification, analog/mixed-signal designers.
• Develop block-level specifications for very high-speed digital circuits.
• Design and verification of high-speed digital circuits.
• Support post-silicon lab bring-up, debug and productization.
• Understand and validate high-speed serial protocols (USB4, PCIe).
• Interact with customers on requirements, design specs, performance results.

Skills

Multi-Gigabit serial transceivers

DDR and memory interfaces

CMOS high-speed design

High-speed digital circuits

Scripting (Python)

RTL coding

Design verification

Education

Masters or Ph.D. in E.E., Communications

MSc in electronics/electrical engineering

Tools

Cadence toolset

Job description

Kandou Bus SA in Lausanne, Switzerland, seeks a Digital Design Engineer to define concepts, design RTL and verify high-speed digital circuits for its MIMO-over-copper platform. You will work with verification and analog/mixed-signal teams to ensure timing, power and area targets, while engaging with customers on specifications and results.

Applicants should have 5–10 years in digital design, experience with Cadence tools, and a Master’s or PhD in E.E.