Senior DFT Engineer: IJTAG, MBIST & ATPG

Kandou Ai; Saint-Sulpice; Vor Ort; CHF 110.000 - 140.000; Vollzeit

Zusammenfassung

Kandou, a leader in high-speed chip-link solutions, seeks a resourceful DFT Engineer based in Lausanne, Switzerland or UK. Join a fast-growing, high-tech scale-up shaping next-gen semiconductor testability.

You will drive hierarchical MBIST and scan insertion, ATPG pattern generation, IJTAG-based validation, and timing-aware pattern simulations. Collaborate with test and production teams to debug and bring up devices at probe and final test.

Qualifikationen

• 5+ years of DFT experience including implementation and simulation.
• Experience with IJTAG methodologies and hierarchical MBIST.
• ATPG pattern generation and fault coverage analysis.
• Timing-aware pattern simulations experience.
• Proficient in SystemVerilog and standard EDA tools for DFT.
• Bachelor-level engineering degree in electronics or related field.

Aufgaben

• Hierarchical MBIST and scan insertion, BSD implementation.
• ATPG pattern generation and coverage analysis.
• Pattern simulations with timing.
• Defining test mode timing constraints and analyzing timing reports.
• Developing cycle accurate functional patterns using IJTAG.
• Collaborating with test and production teams to debug and bring up devices.

Kenntnisse

Communication

Debugging

Automation scripting

Team collaboration

Ausbildung

Bachelor of Engineering in Electronics and Electrical Engineering

Tools

IJTAG tooling

MBIST

Scripting languages

Jobbeschreibung

Kandou, a leader in high-speed chip-link solutions, seeks a resourceful DFT Engineer based in Lausanne, Switzerland or UK. Join a fast-growing, high-tech scale-up shaping next-gen semiconductor testability.

You will drive hierarchical MBIST and scan insertion, ATPG pattern generation, IJTAG-based validation, and timing-aware pattern simulations. Collaborate with test and production teams to debug and bring up devices at probe and final test.