Senior FPGA Engineer - High-Speed Prototyping & Validation

Kandou Bus SA; Saint-Sulpice; On-site; CHF 140,000 - 210,000; Full time

Job summary

Kandou Bus SA in Switzerland is seeking an experienced FPGA Engineer contractor to help prototype high-speed digital designs for PHY/SerDes IP and validate devices in the lab. You will work closely with firmware, digital, verification and lab teams to ensure robust prototype delivery.

With 10+ years in FPGA prototyping, you bring SystemVerilog RTL, Python scripting, and a solid understanding of verification methods such as UVM.

Qualifications

• 10+ years of experience prototyping digital designs in FPGAs.
• Strong RTL coding skills, SystemVerilog preferred.
• Experience with Python scripting for validation.
• Good communicator with strong analytical skills.
• Understanding of verification methodologies, notably UVM.

Responsibilities

• Support FPGA prototyping for high-speed digital designs for PHY/SerDes IP.
• Validate and bring-up devices and FPGAs in the lab.
• Collaborate with Kandou’s Firmware, Digital, Verification and Lab teams.

Skills

FPGA design

RTL SystemVerilog

Python scripting

Communication & teamwork

UVM experience

Job description

Kandou Bus SA in Switzerland is seeking an experienced FPGA Engineer contractor to help prototype high-speed digital designs for PHY/SerDes IP and validate devices in the lab. You will work closely with firmware, digital, verification and lab teams to ensure robust prototype delivery.

With 10+ years in FPGA prototyping, you bring SystemVerilog RTL, Python scripting, and a solid understanding of verification methods such as UVM.