DFT Engineer CH, UK

Kandou Ai; Saint-Sulpice; Vor Ort; CHF 110.000 - 140.000; Vollzeit

Zusammenfassung

Kandou, a leader in high-speed chip-link solutions, seeks a resourceful DFT Engineer based in Lausanne, Switzerland or UK. Join a fast-growing, high-tech scale-up shaping next-gen semiconductor testability.

You will drive hierarchical MBIST and scan insertion, ATPG pattern generation, IJTAG-based validation, and timing-aware pattern simulations. Collaborate with test and production teams to debug and bring up devices at probe and final test.

Qualifikationen

• 5+ years of DFT experience including implementation and simulation.
• Experience with IJTAG methodologies and hierarchical MBIST.
• ATPG pattern generation and fault coverage analysis.
• Timing-aware pattern simulations experience.
• Proficient in SystemVerilog and standard EDA tools for DFT.
• Bachelor-level engineering degree in electronics or related field.

Aufgaben

• Hierarchical MBIST and scan insertion, BSD implementation.
• ATPG pattern generation and coverage analysis.
• Pattern simulations with timing.
• Defining test mode timing constraints and analyzing timing reports.
• Developing cycle accurate functional patterns using IJTAG.
• Collaborating with test and production teams to debug and bring up devices.

Kenntnisse

Communication

Debugging

Automation scripting

Team collaboration

Ausbildung

Bachelor of Engineering in Electronics and Electrical Engineering

Tools

IJTAG tooling

MBIST

Scripting languages

Jobbeschreibung

Challenges are our drive, innovation our calling. We at Kandou are a team of passionate accomplished professionals making a mark in the semiconductor industry. We're an innovative leader in high-speed and energy efficient chip-chip link solutions critical to the evolution of the electronics industry, continuously developing to meet the demands of not just the customers of today, but of tomorrow too. If you love to be part of a high-tech scale-up and are motivated by pushing your limits and challenging the status quo, we have an opportunity for you.

We are actively seeking a resourceful DFT Engineer based in Lausanne, Switzerland or UK

Key Responsibilities:

• Hierarchical MBIST and scan insertion, BSD implementation
• ATPG pattern generation, coverage analysis, converging to high coverage metrics
• Pattern simulations with timing
• Defining test mode timing constraints, analyzing the timing reports and converge timing
• Developing cycle accurate functional patterns using IJTAG methodology
• Closely working with the test and production engineering teams to debug and bring up devices at probe and final test
• Debugging silicon issues

Skills:

• Excellent communication skills, and strong team player with can do type of attitude
• Excellent debugging skills
• Good scripting skills to develop automation

Qualifications:

• 5+ years of DFT experience including implementation, test pattern development, and simulation
• Proven experience in contributing to DFT solution to complex designs
• Experience working with IJTAG methodologies
• Experience with hierarchical MBIST insertion, hierarchical scan insertion and scan compression methodologies
• Experience in ATPG pattern generation for different kinds of fault models, fault coverage analysis and converging to high coverage metrics
• Good debug capabilities in simulating patterns with timing
• Experience with industry standard EDA tools for DFT, timing, and simulation
• Knowledge of System Verilog

Education:

• Bachelor of Engineering in Electronics and Electrical Engineering, Computer Engineering (equivalent or higher)

Find more English Speaking Jobs in Switzerland on Arbeitnow