Senior Digital Design Engineer — High-Speed AI Hardware

Kandou Ai; Saint-Sulpice; Vor Ort; CHF 120.000 - 180.000; Vollzeit

Zusammenfassung

Kandou in Lausanne (St-Sulpice) is seeking a Digital Design Engineer to define analog/digital interfaces, design high-speed digital circuits and verify them across the full flow. You will collaborate with verification, analog and mixed-signal teams to deliver RTL, timing, and post-silicon bring-up.

The role requires 5–10 years in digital design of multi-Gigabit transceivers, CMOS tech, and experience with Cadence tools; strong scripting (Python) and an ownership mindset.

Qualifikationen

• 5-10 years of digital design of key circuits in multi-Gigabit serial data-link transceivers and DDR and memory interfaces.
• Strong background in high-speed digital circuit design in deep-submicron CMOS technologies.
• Experience with design and verification of complex regulation systems and data processing.
• Exposure to Cadence toolset and industry-standard EDA tools.

Aufgaben

• Concept definition and analog to digital interface specification.
• RTL design with basic DFT and IP verification.
• Logic synthesis and timing analysis; collaborate with verification and analog/mixed-signal designers.
• Validation and bring-up of chips in the lab; post-silicon support.
• Interact with customers on requirements, design specs and performance results.

Kenntnisse

Digital circuit design

High-speed serial interfaces

RTL coding

Scripting (Python)

Verification methodologies

Cadence toolset

Lab bring-up

Ausbildung

Master's or Ph.D. in Electrical Engineering

MSc in electronics/electrical engineering

Tools

Cadence toolset

Jobbeschreibung

Kandou in Lausanne (St-Sulpice) is seeking a Digital Design Engineer to define analog/digital interfaces, design high-speed digital circuits and verify them across the full flow. You will collaborate with verification, analog and mixed-signal teams to deliver RTL, timing, and post-silicon bring-up.

The role requires 5–10 years in digital design of multi-Gigabit transceivers, CMOS tech, and experience with Cadence tools; strong scripting (Python) and an ownership mindset.