Remote FPGA Engineer - High-Speed Digital Design Pro

Helvetic Payroll; Vaud; Hybrid; CHF 124,000 - 207,000; Part time

Job summary

Helvetic Payroll seeks an experienced FPGA engineer for a 3-month, 80% assignment. The role centers on FPGA prototyping and validation of high-speed PHY/SerDes IP, working with firmware, digital design, and verification teams.

Remote work is supported, with an initial hybrid period in Lausanne and a preference for continued hybrid or remote collaboration. The ideal candidate has 10+ years in FPGA design, SystemVerilog RTL skills, and proficiency with standard FPGA toolchains, plus Python

Qualifications

• Over 10 years of FPGA design and prototyping experience.
• Experience designing and prototyping FPGA blocks for multi-Gigabit serial/parallel data-link transceivers.
• Excellent RTL coding skills, preferably SystemVerilog.
• Experience with industry-standard FPGA design/simulation/verification tools.
• Python or another scripting language for design validation and tool setup.

Responsibilities

• Support FPGA prototyping for high-speed digital designs related to PHY and SerDes IP.
• Assist in validation and bring-up of devices and FPGAs in the lab.
• Collaborate with Firmware, Digital Design, Verification, and Lab teams.
• Support design validation, testing, and troubleshooting activities.
• Help set up and improve development and validation environments.

Skills

FPGA design

FPGA prototyping

SystemVerilog

RTL coding

Python scripting

high-speed interfaces

verification methodologies

UVM

teamwork

communication

Tools

FPGA design tools

Job description

Helvetic Payroll seeks an experienced FPGA engineer for a 3-month, 80% assignment. The role centers on FPGA prototyping and validation of high-speed PHY/SerDes IP, working with firmware, digital design, and verification teams.

Remote work is supported, with an initial hybrid period in Lausanne and a preference for continued hybrid or remote collaboration. The ideal candidate has 10+ years in FPGA design, SystemVerilog RTL skills, and proficiency with standard FPGA toolchains, plus Python