FPGA Engineer - 3 month contract, CH

Kandou Bus SA; Saint-Sulpice; Vor Ort; CHF 140.000 - 210.000; Vollzeit

Zusammenfassung

Kandou Bus SA in Switzerland is seeking an experienced FPGA Engineer contractor to help prototype high-speed digital designs for PHY/SerDes IP and validate devices in the lab. You will work closely with firmware, digital, verification and lab teams to ensure robust prototype delivery.

With 10+ years in FPGA prototyping, you bring SystemVerilog RTL, Python scripting, and a solid understanding of verification methods such as UVM.

Qualifikationen

• 10+ years of experience prototyping digital designs in FPGAs.
• Strong RTL coding skills, SystemVerilog preferred.
• Experience with Python scripting for validation.
• Good communicator with strong analytical skills.
• Understanding of verification methodologies, notably UVM.

Aufgaben

• Support FPGA prototyping for high-speed digital designs for PHY/SerDes IP.
• Validate and bring-up devices and FPGAs in the lab.
• Collaborate with Kandou’s Firmware, Digital, Verification and Lab teams.

Kenntnisse

FPGA design

RTL SystemVerilog

Python scripting

Communication & teamwork

UVM experience

Jobbeschreibung

We at Kandou are a team of passionate professionals striving to make a mark in the trajectory of the semiconductor industry. Our list of customers reads like a who’s is who of the technology world.If you love to be part of an adventure of a start-up challenging established tech giants and you are a proactive problem-solver who is motivated by pushing your limits and challenging the status quo, we have an opportunity for you.

Kandou is actively seeking a resourcefulFPGAEngineer contractor.

Responsibilities

• Support FPGA prototyping for high speed digital designs for PHY/SerDes IP
• Validation and bring-up of devices and FPGAs in the lab
• Work closely and support Kandou’s Firmware, Digital, Verification and Lab teams

Skills

• FPGAs design/prototyping of blocks for multi-Gigabit serial and parallel data-link transceivers
• Strong RTL coding skills (SystemVerilog preferred)
• Scripting (Python preferred) and tool setup skills.
• Good communicator and team player with strong analytical skills
• Understanding of verification methodologies, in particular UVM, is an advantage.

Experience

• 10+ years’ experience in prototyping digital designs in FPGAs
• Technical background in FPGA design, validation and verification
• Experience in industry standard FPGA tools for design, simulation and verification
• Experience in digital high-speed blocks. High Speed interface competence and/or PCS experience would be a plus
• Experience using Python or other scripting language for design validation