FPGA Engineer – High-Speed Digital Design

Helvetic Payroll; Vaud; Híbrido; CHF 124.000 - 207.000; A tiempo parcial

Descripción de la vacante

Helvetic Payroll seeks an experienced FPGA engineer for a 3-month, 80% assignment. The role centers on FPGA prototyping and validation of high-speed PHY/SerDes IP, working with firmware, digital design, and verification teams.

Remote work is supported, with an initial hybrid period in Lausanne and a preference for continued hybrid or remote collaboration. The ideal candidate has 10+ years in FPGA design, SystemVerilog RTL skills, and proficiency with standard FPGA toolchains, plus Python

Formación

• Over 10 years of FPGA design and prototyping experience.
• Experience designing and prototyping FPGA blocks for multi-Gigabit serial/parallel data-link transceivers.
• Excellent RTL coding skills, preferably SystemVerilog.
• Experience with industry-standard FPGA design/simulation/verification tools.
• Python or another scripting language for design validation and tool setup.

Responsabilidades

• Support FPGA prototyping for high-speed digital designs related to PHY and SerDes IP.
• Assist in validation and bring-up of devices and FPGAs in the lab.
• Collaborate with Firmware, Digital Design, Verification, and Lab teams.
• Support design validation, testing, and troubleshooting activities.
• Help set up and improve development and validation environments.

Conocimientos

FPGA design

FPGA prototyping

SystemVerilog

RTL coding

Python scripting

high-speed interfaces

verification methodologies

UVM

teamwork

communication

Herramientas

FPGA design tools

Descripción del empleo

Assignment: 80%

Duration: 3 months

Start date: ASAP

Location: Remote, with an initial hybrid period in Lausanne

About The Assignment

Our client is a leading technology company developing high-speed connectivity solutions and digital IP. As part of its engineering team, you will support FPGA prototyping, device validation, and the bring-up of high-speed digital designs for PHY and SerDes IP.

Key Responsibilities

• Support FPGA prototyping for high-speed digital designs related to PHY and SerDes IP.
• Contribute to the validation and bring-up of devices and FPGAs in the laboratory.
• Work closely with Firmware, Digital Design, Verification, and Lab teams.
• Support design validation, testing, and troubleshooting activities.
• Contribute to the setup and improvement of development and validation environments.

Required Skills And Experience

• At least 10 years of experience in FPGA design and prototyping.
• Strong experience designing and prototyping FPGA blocks for multi-Gigabit serial and parallel data-link transceivers.
• Excellent RTL coding skills, preferably in SystemVerilog.
• Experience with industry-standard FPGA tools for design, simulation, and verification.
• Experience with Python or another scripting language for design validation and tool setup.
• Strong technical background in FPGA design, validation, and verification.
• Experience with high-speed digital blocks; knowledge of high-speed interfaces and/or PCS is an advantage.
• Good understanding of verification methodologies; experience with UVM is a plus.
• Strong analytical, communication, and teamwork skills.

Working model

The first two weeks will follow a hybrid model, with three days per week on-site in Lausanne and two days remote. The assignment can then be performed fully remotely, although a hybrid setup remains preferred throughout the three-month assignment.