Remote FPGA Engineer – High-Speed Digital Design

Helvetic Payroll; Lausanne; Hybrid; CHF 110,000 - 170,000; Part time

Job summary

Helvetic Payroll is assisting a leading technology company in Lausanne with an 80% FPGA prototyping assignment. This three-month engagement starts ASAP and offers remote work with an initial hybrid period in Lausanne, focusing on high-speed digital designs for PHY and SerDes IP.

The role emphasizes supporting FPGA prototyping, device validation, and lab bring-up, with collaboration across Firmware, Digital Design, Verification, and Lab teams.

Qualifications

• At least 10 years of experience in FPGA design and prototyping.
• Experience designing and prototyping FPGA blocks for multi-Gigabit serial and parallel data-link transceivers.
• Excellent RTL coding skills in SystemVerilog.
• Experience with industry-standard FPGA tools for design, simulation, and verification.
• Experience with Python for design validation and tool setup.
• Strong background in FPGA design, validation, and verification.
• Experience with high-speed interfaces and/or PCS is an advantage.
• Knowledge of verification methodologies; UVM is a plus.
• Strong analytical, communication, and teamwork skills.

Responsibilities

• Support FPGA prototyping for high-speed digital designs related to PHY and SerDes IP.
• Contribute to validation and bring-up of devices and FPGAs in the laboratory.
• Work closely with Firmware, Digital Design, Verification, and Lab teams.
• Support design validation, testing, and troubleshooting activities.
• Contribute to the setup and improvement of development and validation environments.

Skills

FPGA design & prototyping

RTL/SystemVerilog coding

High-speed serial/parallel IP

FPGA verification methods (UVM)

Python scripting for validation

Lab debugging & lab work

Strong communication & teamwork

Tools

FPGA design tools

Simulation tools

Verification tools

Job description

Helvetic Payroll is assisting a leading technology company in Lausanne with an 80% FPGA prototyping assignment. This three-month engagement starts ASAP and offers remote work with an initial hybrid period in Lausanne, focusing on high-speed digital designs for PHY and SerDes IP.

The role emphasizes supporting FPGA prototyping, device validation, and lab bring-up, with collaboration across Firmware, Digital Design, Verification, and Lab teams.