FPGA Design Engineer (VHDL)

Ellisys; Genf; Hybrid; CHF 110,000 - 150,000; Full time

Job summary

Ellisys in Geneva, Switzerland, seeks a highly analytical engineer with a strong programming background in VHDL or Verilog to join our protocol analysis team. You will design software components for protocol analyzers and testers, and handle large data sets with efficient processing.

Candidates should have high-speed logic design experience, familiarity with Xilinx toolchains, and knowledge of USB, Bluetooth or Wi‑Fi protocols.

Qualifications

• Strong programming background in VHDL/Verilog.
• Experience in high-speed logic design.
• Fluent English or French.

Responsibilities

• Designing new software components for our protocol analyzers, traffic exercisers and compliance testers.
• Defining and implementing creative algorithms and infrastructures for capturing, processing, storing and displaying large amount of data.
• Finding clever ways to present complex information.
• Designing robust expert systems to validate complex scenarios.

Skills

VHDL/Verilog

High-speed logic design

Xilinx tools

Gigabit transceivers

Xilinx Zynq SOC

Object oriented design

USB/Bluetooth/Wi-Fi protocols

Analytical

Communication

Team player

English or French

Tools

Xilinx tools suite

Job description

Ellisys is seeking brilliant people, who are highly analytical, capable of thinking “out-of-the-box”, and who are motivated to learn from the best. You will bring a strong programming background to the team, coupled with personal enthusiasm and high energy. Your work will be challenging and diverse and your creativity and proactive approach will be welcomed. You will be contributing to the world's best and most advanced protocol test solution for technologies such as USB, Bluetooth and Wi‑Fi.

• Strong programming background in VHDL or Verilog
• Strong experience in high-speed logic design
• Experience in the Xilinx tools suite is a plus
• Experience in gigabit transceivers, memory controllers, soft processors is a plus
• Experience in Xilinx Zynq SOC is a plus
• Understanding of Object Oriented design is a plus
• USB, Bluetooth, Wi‑Fi or other communication protocol knowledge is a plus
• Must be analytical, creative and a good communicator
• Strong team player
• Fluent English or French

The job:

• Designing new software components for our protocol analyzers, traffic exercisers and compliance testers
• Defining and implementing creative algorithms and infrastructures for capturing, processing, storing and displaying large amount of data
• Finding clever ways to present complex information
• Designing robust expert systems to validate complex scenarios

This position is open in Geneva, Switzerland.