Lead Analog Layout Engineer - High-Speed SerDes & RF

Kandou AI; Saint-Sulpice; On-site; CHF 110,000 - 170,000; Full time

Job summary

Kandou AI in Europe is seeking a Lead Analog Layout Engineer to design and verify analog circuits, cells, blocks and IP for multi-Gigabit, high-speed SerDes links in cutting-edge semiconductor nodes. You will work closely with the design team to translate requirements into robust layouts.

The role emphasizes expertise in high-speed analog layout, PDN and ESD considerations, and collaboration with customers for IP delivery.

Qualifications

• Experience in custom analog layout for multi-Gigabit data-link transceivers.
• Expertise in high-speed analog circuit layout (amplifiers, oscillators, PLLs).
• Understanding layout techniques for high-speed circuits, parasitics, ESD, power grids.

Responsibilities

• Layout and verification of analog circuits, cells, blocks, and IP for multi-Gigabit high speed chip-to-chip links (SerDes up to 28Gb/s).
• Layout and verification of very high-speed analog circuits.
• Interact with design team to implement solutions.
• Support IP and chip level integration.
• Support customers on requirements and IP delivery.
• Exposure to flip-chip package technologies.

Skills

Self-motivated

Communicator

Team player

Semiconductor Physics

Education

Electrical Engineering degree

Tools

Cadence Virtuoso

Spectre/HSpice

Calibre/PVS DRC/LVS

Parasitics extraction & modelling

EM/IR drop/ESD analysis

Job description

Kandou AI in Europe is seeking a Lead Analog Layout Engineer to design and verify analog circuits, cells, blocks and IP for multi-Gigabit, high-speed SerDes links in cutting-edge semiconductor nodes. You will work closely with the design team to translate requirements into robust layouts.

The role emphasizes expertise in high-speed analog layout, PDN and ESD considerations, and collaboration with customers for IP delivery.