Digital ASIC Designer

CERN; Genf; On-site; CHF 90,000 - 130,000; Full time

Job summary

CERN's EP-ESE-ME section seeks a specialist to develop a radiation-tolerant microcontroller ASIC for detectors and accelerator systems. Working with an open-source RISC-V core and the SOCRATES framework, you’ll help deliver robust embedded electronics for harsh environments.

You will participate in requirements, architecture, implementation, verification and post-silicon validation across the full design cycle, focusing on 65 nm or 28 nm CMOS technologies.

Responsibilities

• Analyse application requirements across CERN's accelerator complex and particle physics detector systems to define technical specifications for the microcontroller ASIC.
• Contribute to the architecture, design, and validation of a radiation-tolerant microcontroller ASIC implemented in 65 nm or 28 nm CMOS technology.
• Support the definition of the SoC architecture, including the selection and configuration of an appropriate RISC-V processing core.
• Design, integrate, and validate peripheral IP blocks within the CERN…

Job description

Join CERN's EP-ESE-ME section in the development of a radiation-tolerant microcontroller ASIC for use in future particle physics detectors and accelerator systems. Operating in highly challenging radiation environments, these systems require robust and reliable embedded electronics.

The project is based on an open-source RISC-V processing core and the CERN SOCRATES (System-On-Chip Radiation-Tolerant Ecosystem) framework for fault-tolerant SoC design. The successful candidate will contribute to the full development cycle, from requirements definition and system architecture to implementation, verification, and post-silicon validation.

Your responsibilities:

• Analyse application requirements across CERN's accelerator complex and particle physics detector systems to define technical specifications for the microcontroller ASIC.
• Contribute to the architecture, design, and validation of a radiation-tolerant microcontroller ASIC implemented in 65 nm or 28 nm CMOS technology.
• Support the definition of the SoC architecture, including the selection and configuration of an appropriate RISC-V processing core.
• Design, integrate, and validate peripheral IP blocks within the CERN…