Digital ASIC Designer

Big Science Sweden; Genf; Hybrid; CHF 110.000 - 140.000; Vollzeit

Zusammenfassung

CERN invites applications for a role in the EP-ESE-ME section to develop a radiation-tolerant microcontroller ASIC for detectors and accelerator systems. The position covers the full development cycle, from requirements to post-silicon validation, within the CERN SOCRATES framework.

Applicants should have a master’s degree with 2–6 years experience or a PhD with up to 3 years. Nationalities constrained by CERN policy apply. On-site in Geneva.

Qualifikationen

• Master’s degree in electrical engineering or related field plus 2–6 years of professional experience, or PhD with up to 3 years of experience.
• Experience in radiation-tolerant ASIC/SoC design is highly desirable.
• Proven ability to contribute across the full development cycle: requirements through tapeout.

Aufgaben

• Define technical specifications for the microcontroller ASIC based on application requirements across CERN systems.
• Contribute to architecture, design, and validation of a radiation-tolerant MCU ASIC implemented in 65 nm or 28 nm CMOS.
• Support SoC architecture and selection/configuration of a RISC-V core.
• Design, integrate, and validate peripheral IP blocks within the CERN SOCRATES framework.
• Apply fault-tolerant methods including TMR and SEU mitigation.
• Participate in RTL development, verification, and physical implementation from tapeout to post-silicon validation.

Kenntnisse

Radiation-tolerant ASIC design

RISC-V architecture

Fault-tolerant design

RTL verification

Post-silicon validation

Ausbildung

Master’s degree in Electrical Engineering

PhD in a relevant field

Tools

Verilog/SystemVerilog

Cadence/Synopsys tools

RTL design and verification tools

Jobbeschreibung

Join CERN’s EP-ESE-ME section in the development of a radiation-tolerant microcontroller ASIC for use in future particle physics detectors and accelerator systems. Operating in highly challenging radiation environments, these systems require robust and reliable embedded electronics.

The project is based on an open-source RISC-V processing core and the CERN SOCRATES (System-On-Chip Radiation-Tolerant Ecosystem) framework for fault-tolerant SoC design. The successful candidate will contribute to the full development cycle, from requirements definition and system architecture to implementation, verification, and post-silicon validation

Your responsibilities

• Analyse application requirements across CERN's accelerator complex and particle physics detector systems to define technical specifications for the microcontroller ASIC.
• Contribute to the architecture, design, and validation of a radiation-tolerant microcontroller ASIC implemented in 65 nm or 28 nm CMOS technology.
• Support the definition of the SoC architecture, including the selection and configuration of an appropriate RISC-V processing core.
• Design, integrate, and validate peripheral IP blocks within the CERN SOCRATES framework.
• Apply fault-tolerant design methodologies, including triple modular redundancy (TMR) and single-event upset (SEU) mitigation techniques.
• Participate in design verification activities and physical implementation, from RTL development through to tapeout.
• Contribute to post-silicon testing, characterisation, and validation following chip fabrication.

Be sure to meet the eligibility criteria

• You are a national of aCERN Member State or Associate Member State. Currently, we cannot consider applications from Pakistani, Lithuanian, Latvian, Cypriot and Croatian nationals, as the ceiling defined under Article II.5 of the Associate Membership Agreement has been reached.
• By the application deadline, you have a master’s degree with 2 to 6 years of professional experience since graduation or a PhD with a maximum of 3 years of professional experience since graduation. You are not eligible with only a bachelor’s degree.
• You have never had a CERN fellow or graduate contract before.
• Please pay attention to the additional criteria and requirements for this specific position and mentioned above.