Digital ASIC Designer, EP-ESE-ME

Big Science Sweden; Genf; Hybrid; CHF 120,000 - 150,000; Full time

Job summary

CERN is seeking a highly skilled engineer to develop a radiation-tolerant microcontroller ASIC for use in particle physics detectors and accelerator systems. The role focuses on architecture, RTL, verification, and post-silicon validation within the SOCRATES framework based on a RISC-V core.

The successful candidate will participate in the full development cycle from requirements to tapeout, ensuring robust embedded electronics in challenging radiation environments.

Qualifications

• Master's degree required with 2–6 years of professional experience or PhD with up to 3 years since graduation.
• No bachelor-only applicants are eligible.
• Candidates must be nationals of CERN Member or Associate Member States.
• Please review the specific criteria listed for this position.

Responsibilities

• Analyse application requirements across CERN systems to define technical specs for the microcontroller ASIC.
• Architect, design, and validate a radiation-tolerant MCU ASIC in 65 nm or 28 nm CMOS technology.
• Assist in SoC architecture selection and configuration of a suitable RISC-V core.
• Design, integrate, and verify peripheral IP blocks within the CERN SOCRATES framework.
• Apply fault-tolerant design methods including TMR and SEU mitigation.
• Contribute to RTL development, verification, and tapeout processes.
• Participate in post-silicon validation and device characterization.

Skills

RISC-V core

ASIC design

Radiation-tolerant

CMOS tech

Embedded systems

Education

Master's degree in EE/CS

PhD

Tools

Verilog

VHDL

Job description

Join CERN’s EP-ESE-ME section in the development of a radiation-tolerant microcontroller ASIC for use in future particle physics detectors and accelerator systems. Operating in highly challenging radiation environments, these systems require robust and reliable embedded electronics.

The project is based on an open-source RISC-V processing core and the CERN SOCRATES (System-On-Chip Radiation-Tolerant Ecosystem) framework for fault-tolerant SoC design. The successful candidate will contribute to the full development cycle, from requirements definition and system architecture to implementation, verification, and post-silicon validation.

Your responsibilities

• Analyse application requirements across CERN's accelerator complex and particle physics detector systems to define technical specifications for the microcontroller ASIC.
• Contribute to the architecture, design, and validation of a radiation-tolerant microcontroller ASIC implemented in 65 nm or 28 nm CMOS technology.
• Support the definition of the SoC architecture, including the selection and configuration of an appropriate RISC-V processing core.
• Design, integrate, and validate peripheral IP blocks within the CERN SOCRATES framework.
• Apply fault-tolerant design methodologies, including triple modular redundancy (TMR) and single-event upset (SEU) mitigation techniques.
• Participate in design verification activities and physical implementation, from RTL development through to tapeout.
• Contribute to post-silicon testing, characterisation, and validation following chip fabrication.

Be sure to meet the eligibility criteria

• You are a national of a CERN Member State or Associate Member State . Currently, we cannot consider applications from Pakistani, Lithuanian, Latvian, Cypriot, Croatian and Turkish nationals, as the ceiling defined under Article II.5 of the Associate Membership Agreement has been reached.
• By the application deadline, you have a master’s degree with 2 to 6 years of professional experience since graduation or a PhD with a maximum of 3 years of professional experience since graduation. You are not eligible with only a bachelor’s degree.
• You have never had a CERN fellow or graduate contract before.
• Please pay attention to the additional criteria and requirements for this specific position and mentioned above.