ASIC Digital Designer — Open-Source RTL to Tapeout

CERN; Genf; Hybrid; CHF 58.768 - 64.649; Vollzeit

Benefits dieser Stelle

Monthly stipend tax-free

30 days paid leave + 2 weeks closure

Comprehensive health insurance

CERN Pension Fund

Relocation package

Contract extension up to 36 months

Language training

Zusammenfassung

CERN designs, develops, and operates particle accelerators and experiments. You will join the HSE-TS-IMS Section to design, verify, and bring up the next-generation ASIC front-end using open-source EDA tools, with a focus on RTL to GDSII work.

The role involves collaboration across SoC, analogue, and verification teams in a hybrid work setting. Requirements include hands-on experience with Yosys/OpenROAD/LibreLane, RTL design in Verilog/SystemVerilog, and knowledge of RISC-V.

Qualifikationen

• Hands-on experience with open-source ASIC EDA flows from RTL to GDSII.
• Experience with floorplanning and physical design preparation for tapeout.
• Knowledge of RTL design in VHDL/Verilog/SystemVerilog and testing.

Aufgaben

• Design, simulate, verify the digital architecture of the next-generation ASIC front-end.
• Prepare RTL designs for tapeout using open-source EDA flows.
• Support post-fabrication bring-up, system characterisation, and validation.
• Collaborate with analogue, verification, and SoC integration teams.

Kenntnisse

HDL design

Verilog

SystemVerilog

VHDL

RISC-V

Git

CI/CD

Linux

Python

Teamwork

Ausbildung

Bachelor's degree in Electronics

Master's degree in Electronics

Tools

Yosys

OpenROAD

LibreLane

Jobbeschreibung

CERN designs, develops, and operates particle accelerators and experiments. You will join the HSE-TS-IMS Section to design, verify, and bring up the next-generation ASIC front-end using open-source EDA tools, with a focus on RTL to GDSII work.

The role involves collaboration across SoC, analogue, and verification teams in a hybrid work setting. Requirements include hands-on experience with Yosys/OpenROAD/LibreLane, RTL design in Verilog/SystemVerilog, and knowledge of RISC-V.