Lead RTL Design Engineer for Next-Gen IoT Chips

Sequans Communications Limited; Zürich; Vor Ort; CHF 100.000 - 135.000; Vollzeit

Zusammenfassung

Sequans Communications Limited is hiring for a position within their VLSI team in Zürich. Responsibilities include specifying, designing, and verifying digital blocks for new chipset generations. Candidates should have a degree in computer science or electrical engineering and at least 5 years of experience in ASIC/FPGA development.

Key skills include proficiency in hardware description languages and experience in optimization techniques. The role demands excellent communication skills and the ability to work in a multicultural environment.

Qualifikationen

• At least 5 years of working experience in ASIC and/or FPGA development.
• Experience in multiple clock domains architectures.
• Familiarity with Unix environment.

Aufgaben

• Design (RTL coding) key digital building blocks.
• Requirements analysis and micro architecture definition.
• Contribute to integration, testing and debugging.

Kenntnisse

Hardware description languages (SystemVerilog/Verilog/VHDL)

Optimization techniques for high throughput designs

Front End activities (e.g Lint, CDC, RDC tools)

Programming/scripting (C-Shell, Tcl, Python)

Version control systems (Git, SVN)

Ausbildung

Degree (BSc/MSc/PhD) in computer science or electrical engineering

Tools

Static timing analysis tools

Synthesis tools

Jobbeschreibung

Sequans Communications Limited is hiring for a position within their VLSI team in Zürich. Responsibilities include specifying, designing, and verifying digital blocks for new chipset generations. Candidates should have a degree in computer science or electrical engineering and at least 5 years of experience in ASIC/FPGA development.

Key skills include proficiency in hardware description languages and experience in optimization techniques. The role demands excellent communication skills and the ability to work in a multicultural environment.