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Semtech's Global Test Engineering team is a world-class organization of innovative engineers who enable the success of our entire semiconductor portfolio through cutting‑edge test solutions and methodologies. We are the technical backbone that ensures every Semtech product meets the highest standards of quality, reliability, and performance. Our team spans multiple sites globally and serves as the center of excellence for test innovation, working closely with all business units to deliver breakthrough test capabilities. We specialize in mixed‑signal, high‑speed digital, and RF test development, with particular expertise in advanced SiGe BiCMOS technologies. Our engineers drive competitive advantage through innovative test architectures, methodologies, and continuous improvement initiatives that directly impact Semtech's bottom line.

We are seeking a Principal NPI Test Engineer to serve as the technical authority and strategic leader for new product introduction test development in our mixed‑signal product portfolio. This role demands a proven innovator who can architect comprehensive test solutions spanning from early silicon validation through high‑volume production. The ideal candidate will drive testability standards across the organization, lead complex multi‑disciplinary projects, and deliver breakthrough test methodologies that enable next‑generation high‑speed communication products operating at 200Gbps and beyond.

• Architect and define test strategies for complex mixed‑signal SiGe products from concept through production maturity
• Lead development of innovative test methodologies for high‑speed SerDes, CDRs, and signal conditioning products
• Drive DFT/testability requirements into IC architecture, establishing company‑wide standards and best practices
• Develop and implement advanced test techniques for products operating at >200Gbps data rates
• Create reusable test IP, libraries, and frameworks that accelerate NPI cycles across product families
• Perform technical risk assessment and mitigation strategies for test coverage and quality

• Serve as test engineering authority in product architecture reviews and gate meetings
• Partner with IC design teams from concept phase to ensure optimal test coverage and manufacturability
• Lead test readiness reviews with stakeholders, providing strategic recommendations
• Collaborate with Product Engineering to define characterization strategies and correlation methodologies
• Interface with customer quality teams on test specifications and coverage requirements
• Architect and launch test solutions that achieve test time targets for complex mixed‑signal devices
• Drive continuous improvement initiatives that reduce NPI cycle time by 10‑20%

• Research and implement next‑generation ATE capabilities and measurement techniques
• Develop proprietary test methods that provide competitive advantage in cost and quality
• Lead evaluation and adoption of new test platforms, instrumentation, and methodologies
• Pioneer implementation of AI/ML techniques for yield enhancement and test optimization
• Establish Semtech as industry leader in mixed‑signal test innovation

• Ensure seamless transfer of test solutions to high‑volume OSATs with >99% first‑pass success
• Drive test cost reduction initiatives delivering year‑over‑year improvements
• Establish and monitor KPIs for test effectiveness, efficiency, and quality

• Mentor junior engineers, developing next generation of test leaders
• Create and maintain comprehensive test methodology documentation and training materials
• Build strategic relationships with test partners to influence platform development
• Foster culture of innovation and continuous learning within test organization

• Expert‑level proficiency with Advantest V93000 platform (SmarTest 7/8)
• Advanced programming skills in C/C++, Python, and TCL
• Deep understanding of high‑speed signal integrity, jitter analysis, and BER testing
• Expertise in analog/mixed‑signal DFT techniques (BIST, scan, boundary scan)
• Proficiency in RF/microwave test techniques beyond 40GHz
• Strong foundation in statistical process control and quality methodologies
• Experience with PCB design tools (Cadence, Altium) and signal integrity simulation

• Demonstrated ability to influence without direct authority across organizations
• Track record of delivering complex projects on aggressive schedules
• Strong presentation skills to executive leadership and customers
• Proven ability to build and maintain strategic vendor relationships

• Master's degree or PhD in relevant engineering discipline
• 15+ years in semiconductor test with focus on SerDes/high‑speed I/O
• Experience with SiGe BiCMOS process technology and its test challenges
• Knowledge of automotive quality standards (AEC‑Q100) and qualification flows
• Familiarity with 93000 PS1600/PS3600 digital channels and Wave Scale RF
• Experience with wafer‑level testing and probe card design
• Experience with test data analytics and machine learning applications

• Serves as company‑wide test architecture authority for mixed‑signal products
• Builds test capabilities that enable entry into new markets and applications
• Establishes Semtech's reputation as test innovation leader in high‑speed communications

The intent of this job description is to describe the major duties and responsibilities performed by incumbents of this job. Incumbents may be required to perform job‑related tasks other than those specifically included in this description.

All duties and responsibilities are essential job functions and requirements and are subject to possible modification to reasonably accommodate individuals with disabilities.