Tile PnR Lead: SoC Physical Design Leader

AMD; Markham; On-site; CAD 120,000 - 180,000; Full time

Job summary

AMD in Markham, ON is seeking an experienced Tile PnR Lead to guide the physical implementation of complex SoC tiles from floorplanning to tapeout. You will drive strategy, scheduling, and design quality while mentoring engineers across global teams.

The ideal candidate brings proven Tile PnR leadership, multiple tape-outs, and expertise in timing, PPA optimization, and AI-assisted methodologies to advance AMD's silicon leadership.

Qualifications

• BS/MS in Electrical or Computer Engineering or related field.
• Proven leadership across multiple projects or product families.
• Multiple tape-outs at advanced nodes and tile/IP leadership.

Responsibilities

• Lead physical implementation of complex SoC tiles from floorplan to tapeout.
• Define and drive Tile PnR strategy, including timing closure and PPA.
• Mentor engineers and drive execution with cross-functional teams.
• Champion new methods, automation, and AI-enabled design solutions.

Skills

Tile PnR

Technical Leadership

Global teams

Tape-out experience

AI-assisted design

Education

BS/MS in Electrical Engineering or Computer Engineering

Tools

ICC2

Fusion Compiler

PrimeTime

RedHawk/Totem

Calibre

Job description

AMD in Markham, ON is seeking an experienced Tile PnR Lead to guide the physical implementation of complex SoC tiles from floorplanning to tapeout. You will drive strategy, scheduling, and design quality while mentoring engineers across global teams.

The ideal candidate brings proven Tile PnR leadership, multiple tape-outs, and expertise in timing, PPA optimization, and AI-assisted methodologies to advance AMD's silicon leadership.