Senior ASIC Implementation Engineer - Ultra Low Power AI SoC

Qualcomm; Markham; On-site; CAD 163,000 - 233,000; Full time

Job summary

Qualcomm Technologies Audio division seeks an ASIC Implementation Engineer to deliver ultra-low power, high-performance audio subsystems. You will drive RTL design, synthesis, and timing constraints, while validating power intent and performing STA and CDC checks.

The role involves modeling tradeoffs across architectures and collaborating to refine implementation flows. Applicants should have 2+ years in ASIC design/verification, strong Verilog/VHDL, and experience with Synopsys/Cadence

Qualifications

• Bachelor's degree in Science or Engineering with 2+ years of ASIC design/verification.
• Strong RTL coding in Verilog/VHDL and clean, synthesizable RTL.
• Experience with Synopsys or Cadence toolflows and power analysis.
• Knowledge of UPF and low-power ASIC design concepts is a plus.
• Detail oriented with analytical and debugging skills.

Responsibilities

• Synthesize, implement timing constraints, and create ECOs.
• Power intent validation and STA, lint, and CDC checks.
• Model and analyze performance, area, power tradeoffs.
• Contribute to implementation methodologies and flows.
• May perform RTL development tasks in addition to responsibilities.

Skills

Verilog/VHDL RTL

Power analysis

Synthesis

Clock domain crossing

Scripting (Python, PERL, TCL)

Education

Bachelor's degree in Engineering/Science

Master's degree in Engineering/Science

PhD in Engineering/Science

Tools

Synopsys

Cadence

Power/Timing analysis tools

Job description

Qualcomm Technologies Audio division seeks an ASIC Implementation Engineer to deliver ultra-low power, high-performance audio subsystems. You will drive RTL design, synthesis, and timing constraints, while validating power intent and performing STA and CDC checks.

The role involves modeling tradeoffs across architectures and collaborating to refine implementation flows. Applicants should have 2+ years in ASIC design/verification, strong Verilog/VHDL, and experience with Synopsys/Cadence