Sr Digital Design Engineer

StarIC; Toronto; Hybrid; CAD 85,000 - 120,000; Full time

Benefits offered by this job

Competitive compensation

Hybrid work eligible

Collaborative team across Toronto and 

Job summary

StarIC in Toronto and Utrecht seeks an experienced digital IC design lead to drive block and SoC development from architecture through verification, synthesis, and lab support on mixed-signal and interconnect programs. You will own specifications, RTL design, timing closure, and lab testing, while coordinating with global teams and back-end flows for silicon, FPGAs, and system simulators.

Applicants should have a BSc/MSc in Electronic or Computer Engineering and 3–6 years of digital IC design

Qualifications

• 3–6 years of digital IC design experience (strong academic work considered).
• VHDL and/or Verilog design and simulation experience.
• Front-end flow experience (Synopsys, Cadence, and/or Mentor): verification, synthesis, STA, back-annotation, gate-level simulation.
• Backend flow, floor planning, or close coordination with physical design.
• DSP algorithms and building blocks experience is a strong plus.
• Comfort working with global, cross-functional teams.
• Project management skills are a plus.

Responsibilities

• Lead digital development and design projects end to end.
• Own specification, modeling, RTL, verification, synthesis, timing closure, vectors, simulation, lab testing, layout support, and documentation.
• Maintain and extend existing digital designs, test systems, and supporting software and scripts.
• Run design reviews; support characterization, qualification, and backend flows for silicon, FPGAs, and system simulators.

Skills

RTL design

VHDL/Verilog

Digital IC design

Front-end flows

Back-end flows

DSP algorithms

Cross-functional teamwork

Project management

Education

BSc/MSc in ECE

Tools

Synopsys

Cadence

Mentor

Job description

Join the team engineering electro-photonic silicon for AI, HPC, data centers, and Physical AI, from Toronto and Utrecht.

About the role

Lead digital block and SoC development from architecture through verification, synthesis, and lab support on mixed-signal and interconnect programs.

Responsibilities

• Lead digital development and design projects end to end.
• Own specification, modeling, RTL, verification, synthesis, timing closure, vectors, simulation, lab testing, layout support, and documentation.
• Maintain and extend existing digital designs, test systems, and supporting software and scripts.
• Run design reviews; support characterization, qualification, and backend flows for silicon, FPGAs, and system simulators.

Qualifications

• BSc or MSc in Electronic or Computer Engineering.
• 3–6 years of digital IC design experience (strong academic work considered).
• VHDL and/or Verilog design and simulation experience.
• Front-end flow experience (Synopsys, Cadence, and/or Mentor): verification, synthesis, STA, back-annotation, gate-level simulation.
• Backend flow, floor planning, or close coordination with physical design.
• DSP algorithms and building blocks experience is a strong plus.
• Comfort working with global, cross-functional teams.
• Project management skills are a plus.

Perks and benefits

• Competitive compensation.
• Collaborative, growing team across Toronto and Utrecht.
• Hybrid work eligible for most roles.