Senior FPGA Design Engineer

USA Tech Recruit; Ottawa; On-site; CAD 150,000 - 170,000; Full time

Job summary

USA Tech Recruit seeks a Senior FPGA Design Engineer to join a specialist engineering consultancy client in Ottawa, on-site. You will design high-speed FPGA solutions for a global leader in optical and photonics technology, contributing from specification through timing closure.

This long-term role requires ramping up quickly, owning complex designs, and collaborating with hardware, verification, and systems teams to deliver robust, testable FPGA implementations.

Qualifications

• Approximately 10–15 years of hands-on FPGA design experience.
• Strong and current expertise in SystemVerilog.
• Experience identifying, analyzing and resolving CDC challenges.
• Hands-on experience configuring and managing FPGA synthesis tools.
• Strong understanding of SDC timing constraints and constraint development.
• Proven ability to interpret synthesis and timing reports.

Responsibilities

• Design and implement FPGA logic from architecture to production-ready designs.
• Analyze and manage CDC, including synchronization strategies and verification.
• Own the FPGA synthesis flow and drive timing closure.
• Analyze reports to resolve timing, congestion, and resource issues.
• Collaborate with hardware, verification, and systems teams.
• Participate in design reviews and documentation.
• Improve FPGA design methodologies and practices.
• Progress toward a design prime role.

Skills

SystemVerilog

CDC analysis

FPGA design

Synthesis tool configuration

Timing analysis

Collaboration

Tools

FPGA synthesis tools

SDC timing constraints

CDC tooling

Job description

A specialist engineering consultancy supporting ASIC, FPGA, and embedded software development is expanding its team and is looking for a Senior FPGA Design Engineer to join a long-standing client engagement. You will work on-site with a global leader in optical and photonics technology, contributing to advanced, high-speed products at the forefront of optical networking and communications.

This is a long-term opportunity for an experienced FPGA engineer who can ramp up quickly, take ownership of complex designs with minimal supervision, and grow into a design prime role over the next couple of years. You will work closely with hardware, verification, and systems teams to take FPGA designs from specification and micro-architecture through implementation and timing closure.

This is a full time, onsite position in Ottawa, and you should have full right to work in Canada.

Key Responsibilities:

• Design and implement FPGA logic using SystemVerilog, from micro-architecture through to production-ready, timing-clean designs.
• Analyze and manage clock domain crossings (CDC), including synchronization strategies and CDC verification.
• Own the FPGA synthesis flow, including tool configuration, timing constraints, and driving designs through to timing closure.
• Analyze synthesis and timing reports to identify and resolve timing, congestion, and resource utilization issues.
• Collaborate closely with hardware, verification, and systems engineering teams to ensure designs are robust, testable, and implementation-friendly.
• Participate in design reviews and technical documentation.
• Contribute to improving FPGA design methodologies, processes, and best practices.
• Take increasing technical ownership with the opportunity to progress toward a design prime position.

Key Qualifications:

• Approximately 10–15 years of hands-on FPGA design experience, with the technical depth to ramp up quickly and take ownership of complex designs.
• Strong and current expertise in SystemVerilog.
• Practical experience identifying, analyzing, and resolving clock domain crossing (CDC) challenges.
• Hands-on experience configuring and managing FPGA synthesis tools.
• Strong understanding of SDC timing constraints and constraint development.
• Proven ability to interpret synthesis and timing reports and translate findings into effective design changes.
• Experience taking FPGA designs through implementation and achieving timing closure.
• Strong communication and collaboration skills across hardware, verification, and systems teams.
• Ability and willingness to work full-time on-site in Ottawa, Canada.
• Legally eligible to work in Canada.

Nice to Have:

• Exposure to UVM-based verification.
• Scripting experience with Tcl, Python, or similar tools to automate and support FPGA design flows.
• Familiarity with high-speed interfaces used in optical networking, communications, or photonics products.

The role offers a salary of CAD $150,000–$170,000 per year, plus bonus and benefits, with final compensation dependent on experience and technical capability.

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