Senior FPGA Engineer

European Recruitment BV; Ottawa; On-site; CAD 120,000 - 180,000; Full time

Job summary

European Recruitment BV is seeking an experienced FPGA Design Engineer to join our Ottawa team. You’ll own FPGA designs from specification through implementation, partnering with hardware, verification, and systems groups to deliver robust, production-quality solutions.

This full-time, on-site role offers a path to leadership as you grow toward a Design Prime role within a few years. You will design using SystemVerilog, manage CDC, optimize timing, and drive timing closure through synthesis

Qualifications

• 10-15 years of hands-on FPGA design experience.
• Strong, current experience with SystemVerilog.
• Practical experience with CDC analysis and implementation.
• Hands-on experience configuring FPGA synthesis tools.
• Strong understanding of SDC timing constraints and constraint development.
• Proven ability to analyse synthesis/timing reports and drive designs through timing closure.
• Ability to work full-time, on-site in Ottawa.

Responsibilities

• Design and implement FPGA logic using SystemVerilog, from micro-architecture through timing-clean implementation.
• Analyse and manage Clock Domain Crossings (CDC) including synchronization strategies and CDC verification.
• Own the FPGA synthesis flow, including tool configuration, timing constraints, and timing closure.
• Analyse synthesis and timing reports to resolve timing, congestion, and resource utilisation issues.
• Collaborate with hardware, verification, and systems teams to ensure robust, testable designs.
• Contribute to design reviews, technical documentation, and improvements to FPGA design processes.

Skills

SystemVerilog

CDC analysis

FPGA synthesis tools

SDC timing constraints

Timing closure

On-site Ottawa

UVM verification

Tcl scripting

Python scripting

Job description

We’re looking for an experienced FPGA Design Engineer to join a growing engineering team in Ottawa. You’ll take ownership of FPGA designs from specification through implementation, working closely with hardware, verification, and systems teams to deliver robust, production-quality solutions.

This is a full-time, on-site position in Ottawa, ideal for someone looking for a stable, long-term opportunity with the potential to grow into a Design Prime role within the first few years.

Key Responsibilities

• Design and implement FPGA logic using SystemVerilog, from micro-architecture through to timing-clean implementation.
• Analyse and manage Clock Domain Crossings (CDC), including synchronization strategies and CDC verification.
• Own the FPGA synthesis flow, including tool configuration, timing constraints, and timing closure.
• Analyse synthesis and timing reports to identify and resolve timing, congestion, and resource utilisation issues.
• Collaborate with hardware, verification, and systems teams to ensure designs are robust, testable, and implementation-ready.
• Contribute to design reviews, technical documentation, and improvements to FPGA design processes.

Must-Have Experience

• 10-15 years of hands-on FPGA design experience, with the ability to quickly take ownership of complex designs.
• Strong, current experience with SystemVerilog.
• Practical experience with CDC analysis and implementation.
• Hands-on experience configuring FPGA synthesis tools.
• Strong understanding of SDC timing constraints and constraint development.
• Proven ability to analyse synthesis/timing reports and drive designs through timing closure.
• Ability to work full-time, on-site in Ottawa.

Nice to Have

• Experience with UVM-based verification.
• Scripting experience with Tcl, Python, or similar.
• Familiarity with high-speed interfaces used in optical, networking, or communications products.