Hybrid Senior Security IP Architect for SoC Hardware

Arm; Toronto; Híbrido; CAD 126.000 - 170.000; Jornada completa

Descripción de la vacante

Arm is seeking Security Hardware Designers for its Solutions Engineering Security IP Team in Canada. The role focuses on architecture, RTL design, and verification of security subsystems within SoCs, including cryptography, secure boot, and key management.

You will develop architectures, collaborate across verification and implementation teams, and mentor colleagues while advancing design processes and roadmaps across projects.

Formación

• Bachelor's or Graduate degree in Computer Science or Electrical/Computer Engineering.
• Proven ownership and leadership in design and productization of Compute, Multimedia, or Security Sub-Systems and SoCs.
• Strong background in hardware Verilog RTL design, verification, and EDA methodologies.

Responsabilidades

• Architect, specify, RTL and constraint development for security hardware functions.
• Collaborate with verification and implementation peers to build test plans and drive verification closure.
• Mentor team members and balance project management, roadmaps, initiatives, and schedules.
• Lead design exploration, optimization, and structural checks; contribute to processes and methodologies.

Conocimientos

Verilog RTL design

Security hardware

SoC architecture

Synthesis & timing

CDC/RDC/LINT

Power management

Scripting languages

Educación

Bachelor's or Graduate degree in CS or ECE

Herramientas

SystemVerilog

UVM/OVM

Portable Stimulus

Hardware/Firmware co-verification

Descripción del empleo

Arm is seeking Security Hardware Designers for its Solutions Engineering Security IP Team in Canada. The role focuses on architecture, RTL design, and verification of security subsystems within SoCs, including cryptography, secure boot, and key management.

You will develop architectures, collaborate across verification and implementation teams, and mentor colleagues while advancing design processes and roadmaps across projects.