Senior Digital Design Engineer, PCIe/Ethernet IP & SoC

Astera Labs; Toronto; On-site; CAD 140,000 - 155,000; Full time

Benefits offered by this job

Discretionary bonus

Benefits

Job summary

Astera Labs is seeking a Senior Digital Design Engineer to design high-performance connectivity silicon for AI infrastructure. You will work on PCIe and Ethernet controllers, bridges, and SerDes IP, delivering robust RTL and scalable designs across advanced process nodes.

Join cross-functional teams to translate complex connectivity requirements into production-ready solutions, participate in integration and timing closure, and help accelerate time-to-market for rack-scale AI systems in Canada.

Qualifications

• Bachelor's degree in Electrical Engineering or related field.
• 2–5 years of digital design and implementation experience.
• Hands-on RTL experience in SystemVerilog or Verilog, including synthesis and timing closure.
• Experience with PCIe or Ethernet controller, bridge, switch, or SerDes IP.
• Frontend design, gate-level simulation, clock-domain crossing, lint, or related methodologies.
• Proficiency with Python or Perl to automate workflows.
• Authorized to work in Canada.

Responsibilities

• Design and implement RTL for PCIe/Ethernet controllers, bridges, switches, and SerDes IP.
• Translate architecture requirements into scalable, synthesizable designs using SystemVerilog/Verilog.
• Own block-level and full-chip design deliverables from spec to GDS handoff.
• Contribute to 16 nm or smaller nodes, including PCIe Gen 6/7 and UALink/UCI as applicable.
• Drive synthesis, timing analysis, timing closure, and design-quality reviews.
• Collaborate with verification, firmware, and system teams to close gaps and improve IP.
• Support gate-level simulation, emulation, pre- and post-silicon activities.

Skills

SystemVerilog

Verilog

Python

RTL design

Education

Bachelor's degree in Electrical Engineering

Tools

Synopsys

Cadence

Python

Perl

Job description

Astera Labs is seeking a Senior Digital Design Engineer to design high-performance connectivity silicon for AI infrastructure. You will work on PCIe and Ethernet controllers, bridges, and SerDes IP, delivering robust RTL and scalable designs across advanced process nodes.

Join cross-functional teams to translate complex connectivity requirements into production-ready solutions, participate in integration and timing closure, and help accelerate time-to-market for rack-scale AI systems in Canada.