Lead High-Speed Analog Layout Engineer

Emploive; Ottawa; Hybrid; CAD 120,000 - 180,000; Full time

Benefits offered by this job

Foundational role at a startup

International team culture

Cross-functional collaboration

Growth opportunities

Job summary

Celero Communications is seeking a High-Speed Analog Layout Design Engineer to drive the layout of complex analog/mixed-signal IP blocks for advanced optical systems. You will lead floor planning through final verification, collaborating with circuit designers and CAD/PDK teams to ensure first-pass silicon success.

You will mentor other layout engineers across multiple time zones and contribute to top-level planning, power grid design, and signoff checks, while supporting automation through

Qualifications

• Minimum 10+ years of analog/mixed-signal layout experience in advanced CMOS/FinFET technologies.
• Proven IP layout macro or full-chip layout leadership with handoff to Physical Design.
• Experience with TSMC FinFET nodes (N3/N5/N7/N16) and layout verification flows (LVS/DRC/PEC/ERC).

Responsibilities

• Lead physical layout of complex analog/mixed-signal macros from floor planning to verification.
• Collaborate with schematic designers to optimize layout for performance, matching, symmetry, and reliability.
• Mentor junior layout engineers across time zones and promote best practices.
• Perform LVS, DRC, PEC, ERC checks and contribute to layout reviews and automation efforts.

Skills

Analog/mixed-signal layout

IP/layout macro leadership

Collaboration across time zones

Mentoring engineers

Layout verification knowledge

Revision control usage

Tools

Cadence Virtuoso

Calibre

Pegasus

SKILL

Python

TCL

Job description

Celero Communications is seeking a High-Speed Analog Layout Design Engineer to drive the layout of complex analog/mixed-signal IP blocks for advanced optical systems. You will lead floor planning through final verification, collaborating with circuit designers and CAD/PDK teams to ensure first-pass silicon success.

You will mentor other layout engineers across multiple time zones and contribute to top-level planning, power grid design, and signoff checks, while supporting automation through