Senior High-Speed Analog Layout Architect

Celero Communications, Inc.; Ottawa; On-site; CAD 120,000 - 180,000; Full time

Job summary

Celero Communications, Inc. seeks a Principal High-Speed Analog Layout Design Engineer to lead the layout of analog and mixed-signal IP blocks for advanced optical systems. You will own floor planning, routing, and signoff checks, collaborating with circuit designers and CAD/PDK teams.

The role requires mentoring junior engineers across time zones and delivering first-pass silicon through LVS/DRC/ER, with hands-on work in Cadence Virtuoso and related tools.

Qualifications

• 10+ years of hands-on analog/mixed-signal layout experience.
• Experience with top-level IP layout macros and handoff to Physical Design.
• Leadership in owning IP layout macros or full-chip-level layouts at FinFET nodes.
• At least 1 year with TSMC FinFET nodes (N3/N5/N7/N16).
• Deep understanding of device physics and layout-dependent effects.

Responsibilities

• Lead and own the physical layout design of complex analog/mixed-signal macros from floor planning through verification.
• Collaborate with schematic designers to optimize layout performance, matching, symmetry and reliability.
• Mentor junior layout engineers across multiple time zones, enforcing best practices.
• Perform and debug LVS, DRC, PERC, ERC and other checks using industry tools.
• Contribute to chip-level planning including top-level floor planning and power grid design.
• Participate in layout design reviews and provide technical leadership for quality and schedule.
• Support automation through scripting and tool customization (SKILL, TCL, Python a plus).

Skills

Analog layout

Mixed-signal design

CMOS/FinFET

IP layout

Floor planning

LVS/DRC

Scripting

Mentoring

Leadership

Routing & power grid

Tools

Cadence Virtuoso

Job description

Celero Communications, Inc. seeks a Principal High-Speed Analog Layout Design Engineer to lead the layout of analog and mixed-signal IP blocks for advanced optical systems. You will own floor planning, routing, and signoff checks, collaborating with circuit designers and CAD/PDK teams.

The role requires mentoring junior engineers across time zones and delivering first-pass silicon through LVS/DRC/ER, with hands-on work in Cadence Virtuoso and related tools.