Senior High-Speed Analog Layout Architect

Celero Communications, Inc.; Ottawa; On-site; CAD 140,000 - 190,000; Full time

Benefits offered by this job

Foundational role

International team

Growth opportunities

Job summary

Celero Communication Inc. is seeking a Principal/Senior Analog Layout Engineer to drive the layout design of complex analog/mixed-signal IP blocks for high-speed optical communication systems.

You will lead floor planning, block integration, and signoff checks, interfacing with circuit designers and CAD/PDK teams. The role requires mentoring junior engineers across time zones and delivering first-pass silicon by enforcing best practices in layout verification and optimization.

Qualifications

• Minimum 10+ years of hands-on analog/mixed-signal layout design experience in advanced CMOS/FinFET technologies.

Responsibilities

• Lead and own the physical layout design of complex analog/mixed-signal macros (e.g., ADCs, DACs, PLLs), from floor planning through final verification.
• Collaborate with schematic designers to create optimal layout solutions considering performance, matching, symmetry, and reliability.
• Mentor and guide junior layout engineers/contractors across multiple time zones, enforcing best practices in layout design and verification.
• Perform and debug full hierarchy LVS, DRC, PERC, ERC, and other signoff checks using industry-standard tools (Pegasus, Calibre, etc.).
• Contribute to chip-level planning including top-level floor planning, block integration, power grid implementation, and signal routing.

Skills

Analog/mixed-signal layout design

Leadership & mentoring

Cross-functional collaboration

Documentation

Tools

Cadence Virtuoso

Calibre

Pegasus

LVS/DRC/PERC verification

Job description

Celero Communication Inc. is seeking a Principal/Senior Analog Layout Engineer to drive the layout design of complex analog/mixed-signal IP blocks for high-speed optical communication systems.

You will lead floor planning, block integration, and signoff checks, interfacing with circuit designers and CAD/PDK teams. The role requires mentoring junior engineers across time zones and delivering first-pass silicon by enforcing best practices in layout verification and optimization.