Principal High-Speed Analog Layout Design Engineer | Irvine, CA

Celero Communications, Inc.; Ottawa; On-site; CAD 120,000 - 180,000; Full time

Job summary

Celero Communications, Inc. seeks a Principal High-Speed Analog Layout Design Engineer to lead the layout of analog and mixed-signal IP blocks for advanced optical systems. You will own floor planning, routing, and signoff checks, collaborating with circuit designers and CAD/PDK teams.

The role requires mentoring junior engineers across time zones and delivering first-pass silicon through LVS/DRC/ER, with hands-on work in Cadence Virtuoso and related tools.

Qualifications

• 10+ years of hands-on analog/mixed-signal layout experience.
• Experience with top-level IP layout macros and handoff to Physical Design.
• Leadership in owning IP layout macros or full-chip-level layouts at FinFET nodes.
• At least 1 year with TSMC FinFET nodes (N3/N5/N7/N16).
• Deep understanding of device physics and layout-dependent effects.

Responsibilities

• Lead and own the physical layout design of complex analog/mixed-signal macros from floor planning through verification.
• Collaborate with schematic designers to optimize layout performance, matching, symmetry and reliability.
• Mentor junior layout engineers across multiple time zones, enforcing best practices.
• Perform and debug LVS, DRC, PERC, ERC and other checks using industry tools.
• Contribute to chip-level planning including top-level floor planning and power grid design.
• Participate in layout design reviews and provide technical leadership for quality and schedule.
• Support automation through scripting and tool customization (SKILL, TCL, Python a plus).

Skills

Analog layout

Mixed-signal design

CMOS/FinFET

IP layout

Floor planning

LVS/DRC

Scripting

Mentoring

Leadership

Routing & power grid

Tools

Cadence Virtuoso

Job description

Principal High-Speed Analog Layout Design Engineer

We are seeking aHigh-Speed Analog Layout Design Engineerto drive the layout design of complex analog and mixed-signal IP blocks that are at the heart of our advanced optical communication systems. As a key member of the Analog & Mixed-Signal (AMS) design team, you will lead layout development of critical blocks such as ADCs, DACs, PLLs, and other high-performance analog/mixed-signal circuits. You will interface closely with circuit designers, CAD/PDK teams, and other layout engineers to ensure first-pass silicon success. This is a hands-on technical role ideal for someone who thrives in a fast-paced environment and enjoys mentoring others while contributing directly to cutting-edge chip development.

Key Responsibilities

• Lead and own the physical layout design of complex analog/mixed-signal macros (e.g., ADCs, DACs, PLLs), from floor planning through final verification
• Collaborate closely with schematic designers to create optimal layout solutions considering performance, matching, symmetry, and reliability
• Mentor and guide junior layout engineers/contractors across multiple time zones, enforcing best practices in layout design and verification
• Perform and debug full hierarchy LVS, DRC, PERC, ERC, and other signoff checks using industry-standard tools (Pegasus, Calibre, etc.)
• Contribute to chip-level planning including top-level floor planning, block integration, power grid implementation, and signal routing
• Participate in layout design reviews and provide technical leadership for layout quality, verification completeness, and schedule adherence
• Support automation initiatives through scripting and tool customization (SKILL, TCL, Python is a plus)

Required Qualifications

• Minimum 10+ years of hands-on analog/mixed-signal layout design experience and in advanced CMOS/FinFET technologies
• Proven track record of top-level integration IP layout macros and preparing IPs for handoff to Physical Design
• Proven leadership in owning major IP layout macros or full-chip-level layout at FinFET nodes (TSMC preferred)
• At least 1 year of experience with TSMC FinFET process nodes (N3, N5, N7, or N16)
• Deep understanding of device physics, layout-dependent effects (LOD, WPE, OSE, LDE, etc.), and their impact on circuit performance
• Strong expertise in layout best practices for device matching, noise isolation, ESD protection, symmetry, and parasitic minimization
• Proficiency in floor planning, hierarchical block integration, routing strategy, and power/ground grid design
• Expertise with Cadence Virtuoso,