Senior ASIC Verification Engineer - Interface IP & UVM Lead

Synopsys Inc; Markham; On-site; CAD 90,000 - 130,000; Full time

Job summary

Synopsys Inc. seeks an enthusiastic ASIC Digital Design Verification Engineer to verify Interface IP protocols and drive robust verification environments.

You will collaborate with design teams to identify and fix issues, develop comprehensive test plans, and mentor junior engineers in modern verification methodologies. As part of a dynamic team, you will apply SystemVerilog, UVM, and SVA to deliver high-quality IP solutions, documenting results and participating in reviews to ensure overall

Qualifications

• Experience in ASIC digital verification with Interface IP protocols.
• Develop testbenches using SystemVerilog and UVM.
• Mentor junior verification engineers and share best practices.

Responsibilities

• Designing and implementing verification environments for Interface IP protocols to ensure correctness.
• Collaborating with design and architecture teams to identify and fix bugs.
• Performing test plans, functional coverage analysis, and driving coverage closure for complex IP.
• Mentoring junior verification engineers in verification methodologies and best practices.
• Conducting design and verification reviews and providing constructive feedback to improve quality.
• Documenting design specifications, test plans, and verification reports.
• Proficiency in System Verilog, UVM, SVA, and related verification techniques.
• Strong understanding of digital design and verification concepts.
• Excellent problem-solving and communication skills.

Skills

ASIC Digital Verification

Interface IP Protocols

Strong communication

Mentoring

Education

Bachelor's degree in Electrical Engineering or Computer Science

Tools

SystemVerilog

UVM

SVA

Python

Perl

Job description

Synopsys Inc. seeks an enthusiastic ASIC Digital Design Verification Engineer to verify Interface IP protocols and drive robust verification environments.

You will collaborate with design teams to identify and fix issues, develop comprehensive test plans, and mentor junior engineers in modern verification methodologies. As part of a dynamic team, you will apply SystemVerilog, UVM, and SVA to deliver high-quality IP solutions, documenting results and participating in reviews to ensure overall