FPGA Design Engineer – FPGA / SystemVerilog / CDC / Synthesis / Timing Closure / Digital Design

European Tech Recruit; Ottawa; On-site; CAD 120,000 - 160,000; Full time

Job summary

European Tech Recruit is partnering with a growing hardware and communications technology firm to hire an experienced FPGA Design Engineer to own FPGA designs from specification through timing closure. The role emphasizes SystemVerilog design, CDC analysis, and production-quality implementation within a fast-paced engineering team.

You will translate specifications into robust architectures, manage CDC, and ensure reliable FPGA synthesis and timing closure while collaborating with hardware and

Qualifications

• 10–15 years hands-on FPGA design experience or equivalent depth of practical FPGA engineering experience.
• Strong experience developing FPGA designs using SystemVerilog.
• Proven ability to own complex FPGA designs and deliver through implementation.
• Experience with CDC analysis and implementation.
• Experience developing and implementing FPGA synchronization strategies.
• Hands-on experience configuring and managing FPGA synthesis tools.
• Experience with UVM-based verification environments.
• Experience developing automation and engineering scripts using Tcl, Python, or similar languages.
• Familiarity with high-speed digital interfaces.

Responsibilities

• Design and implement FPGA logic using SystemVerilog
• Translate specifications into robust FPGA micro-architectures and production-quality implementations
• Take ownership of FPGA designs through the complete development lifecycle
• Develop timing-clean FPGA implementations and drive designs through timing closure
• Analyse and manage Clock Domain Crossings (CDC)
• Develop appropriate synchronization strategies and ensure reliable clock-domain interfaces
• Perform CDC analysis and contribute to CDC verification activities
• Own and maintain the FPGA synthesis flow

Skills

SystemVerilog

CDC analysis

CDC implementation

FPGA synthesis tools

UVM verification

Tcl scripting

Python scripting

High-speed interfaces

Timing closure

Design ownership

Tools

Synthesis tools

Job description

FPGA Design Engineer – FPGA / SystemVerilog / CDC / Synthesis / Timing Closure / Digital Design

We are currently partnered with a growing technology and engineering organisation developing advanced hardware and communications solutions. As part of their continued expansion, they are looking to hire an experienced FPGA Design Engineer to take ownership of FPGA designs from initial specification and micro-architecture through implementation, synthesis, timing closure, and production.

Key responsibilities

• Design and implement FPGA logic using SystemVerilog
• Translate specifications into robust FPGA micro-architectures and production-quality implementations
• Take ownership of FPGA designs through the complete development lifecycle
• Develop timing-clean FPGA implementations and drive designs through timing closure
• Analyse and manage Clock Domain Crossings (CDC)
• Develop appropriate synchronization strategies and ensure reliable clock-domain interfaces
• Perform CDC analysis and contribute to CDC verification activities
• Own and maintain the FPGA synthesis flow

Key requirements

• 10–15 years of hands‑on FPGA design experience or equivalent depth of practical FPGA engineering experience
• Strong and current experience developing FPGA designs using SystemVerilog
• Proven ability to take ownership of complex FPGA designs and deliver them through implementation
• Strong practical knowledge of Clock Domain Crossing (CDC) analysis and implementation
• Experience developing and implementing FPGA synchronization strategies
• Hands‑on experience configuring and managing FPGA synthesis tools
• Experience with UVM‑based verification environments
• Experience developing automation and engineering scripts using Tcl, Python, or similar languages
• Familiarity with high-speed digital interfaces

Keywords

FPGA Design Engineer / FPGA Engineer / FPGA Design / FPGA Development / Digital Design / Digital Logic / SystemVerilog / RTL / RTL Design / FPGA Micro-Architecture / Clock Domain Crossing / CDC / CDC Analysis / CDC Verification / Synchronisation / FPGA Synthesis / Synthesis Tools / Timing Constraints / SDC / Static Timing Analysis / Timing Analysis / Timing Closure / Timing Optimisation / Congestion / Resource Utilisation / Hardware Design / Digital Electronics / UVM / FPGA Verification / Functional Verification / Tcl / Python / Design Automation / High-Speed Interfaces / High-Speed Digital Design / Optical Communications / Networking / Communications Products / Communications Systems / Production FPGA / Hardware Integration / Systems Engineering / Technical Design / Design Reviews / Technical Documentation / Design Ownership / Design Lead / Design Prime / FPGA Development Flow / FPGA Implementation / FPGA Timing / Hardware Engineering / Embedded Hardware

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