RTL Design Engineer

Advanced Micro Devices; Markham; Hybrid; CAD 100,000 - 150,000; Full time

Job summary

Advanced Micro Devices in Markham, Ontario is seeking a RTL Design Engineer to advance cutting-edge silicon. You will contribute to RTL/IP design for PCIe-related subsystems, collaborate across architecture, verification, physical design, and post-silicon teams, and provide technical leadership throughout the ASIC lifecycle.

The role emphasizes strong RTL/Verilog expertise, PCIe/IP experience, and the ability to drive complex design issues to resolution in a fast-paced environment.

Qualifications

• Bachelor's or Master's in Electrical/Computer Engineering or related field.
• Experience with RTL/Verilog for ASIC design.
• Proven PCIe IP design or support experience.
• Familiarity with ASIC design flows and verification.
• Experience with VCS or similar simulators.

Responsibilities

• Provide technical leadership for ASIC architecture, IP development, and end-to-end design execution.
• Develop, review, and optimize RTL and IP logic designs to meet functional, performance, power, and quality objectives.
• Partner with architecture, design verification, FEINT design, physical design, and integration teams to resolve design issues.
• Support the integration of IP and subsystem-level designs into complex silicon products.
• Review code coverage results, identify coverage gaps, and debug regression failures with verification teams.
• Contribute to design reviews and drive complex technical issues to resolution throughout the development lifecycle.
• Provide post-silicon support to enable successful bring-up, investigate silicon issues, and contribute to yield-learning activities.
• Collaborate across pre-silicon and post-silicon teams to support first-pass silicon success.
• Provide technical guidance and share design knowledge with team members and cross-functional partners.

Skills

RTL design

Verilog

PCIe IP

IP development

VCS

Shell scripting

Perl

Low-power design

Education

Bachelor's or Master's in Electrical/Computer Engineering

Tools

VCS

Perl

Shell

Job description

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believetechnology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMDis shapingthefuture.

Whetheryou’redesigning next-gen processors, enabling AI breakthroughs, orbringing leading edge products to market, every role at AMD contributes to something bigger— technologythat moves the world forward.Join us and, together, we’ll advance your career.

THE ROLE:

As a RTL Design Engineer on the T&E NBIO/PCIe Subsystem team, you will help bring cutting-edge silicon designs to life. You will contribute to RTL and IP logic design while collaborating closely with architecture, design verification, FEINT design, physical design, and post-silicon engineering teams. In this highly collaborative role, you will provide technical leadership throughout the ASIC design lifecycle, help resolve complex design challenges, and support the delivery of robust, high-quality IP. Your work will contribute directly to first-pass silicon success and successful post-silicon bring-up.

THE PERSON:

You are a highly accurate and detail-oriented silicon design professional with strong analytical and problem-solving skills. You communicate effectively across multidisciplinary engineering teams, take ownership of complex technical challenges, and collaborate well with senior team members and technical partners. You thrive in a fast-paced design environment, demonstrate sound technical judgment, and are motivated by delivering high-quality silicon solutions.

KEY RESPONSIBILITIES:

• Provide technical leadership for ASIC architecture, IP development, and end-to-end design execution.
• Develop, review, and optimize RTL and IP logic designs to meet functional, performance, power, and quality objectives.
• Partner with architecture, design verification, FEINT design, physical design, and integration teams to resolve design issues.
• Support the integration of IP and subsystem-level designs into complex silicon products.
• Review code coverage results, identify coverage gaps, and debug regression failures in collaboration with verification teams.
• Contribute to design reviews and drive complex technical issues to resolution throughout the development lifecycle.
• Provide post-silicon support to enable successful bring-up, investigate silicon issues, and contribute to yield-learning activities.
• Collaborate across pre-silicon and post-silicon teams to support first-pass silicon success.
• Provide technical guidance and share design knowledge with team members and cross-functional partners.

PREFERRED EXPERIENCE:

• Strong experience with ASIC design flows, ASIC architecture, and IP development.
• Demonstrated expertise in RTL and IP logic design using Verilog.
• Experience designing or supporting high-speed protocol and controller IP, particularly PCI Express, PCIe subsystem designs, or SerDes PHY technologies.
• Experience with VCS or similar simulation and verification tools.
• Experience reviewing code coverage results and debugging design regressions.
• Proficiency with Perl, Shell, or similar scripting languages used to support design and verification workflows.
• Experience with low-power design techniques and methodologies.
• Understanding of design requirements related to performance, power, area, timing, and functional quality.
• Experience collaborating with architecture, verification, physical design, integration, and post-silicon engineering teams.
• Ability to provide technical direction and drive complex design issues to closure.

ACADEMIC CREDENTIALS:

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field is preferred.

LOCATION:

Markham, Ontario, CA

Benefits offered are described: AMD benefits at a glance.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.