Senior ASIC Digital Design Lead — SERDES PHY IP

Synopsys, Inc.; Mississauga; On-site; CAD 180,000 - 260,000; Full time

Benefits offered by this job

Health benefits

Total rewards package

Job summary

Synopsys, Inc. seeks a visionary technical leader to guide SERDES PHY IP development from concept to customer-ready products.

You will oversee a diverse engineering team, collaborating across architecture, verification, physical implementation, and firmware to meet aggressive timing, power, and performance targets. We value deep expertise in Verilog/SystemVerilog, frontend design flows, and a proven record of mentoring top talent.

Qualifications

• Bachelor’s degree or higher in Electrical Engineering; 15+ years in complex technical development.
• Minimum 2 years’ experience in people management.
• Proficiency in Verilog and SystemVerilog design concepts.
• Strong front-end flows knowledge: linting, synthesis, STA, CDC/RDC, DFT, and power optimization.
• Excellent communication; able to work independently and with cross-functional teams.
• Understanding PCIe and Ethernet is a plus.

Responsibilities

• Lead a diverse design engineering team for next-generation SERDES PHY IP.
• Collaborate with architects, verification, physical implementation, and firmware teams.
• Plan and drive all phases of SERDES PHY IP design from spec to productization and support.
• Ensure timing, performance, and power goals across multiple design cycles.
• Mentor and develop team members, fostering innovation.
• Engage customers for successful IP integration into SoCs and address challenges.

Skills

Verilog / SystemVerilog

Front-end flows

People management

Mentoring

Leadership

PCIe / Ethernet knowledge

Education

Bachelor’s degree in Electrical Engineering

Tools

EDA tools

Job description

Synopsys, Inc. seeks a visionary technical leader to guide SERDES PHY IP development from concept to customer-ready products.

You will oversee a diverse engineering team, collaborating across architecture, verification, physical implementation, and firmware to meet aggressive timing, power, and performance targets. We value deep expertise in Verilog/SystemVerilog, frontend design flows, and a proven record of mentoring top talent.