ASIC Digital Design, Sr Manager-18730

Synopsys, Inc.; Mississauga; On-site; CAD 180,000 - 260,000; Full time

Benefits offered by this job

Health benefits

Total rewards package

Job summary

Synopsys, Inc. seeks a visionary technical leader to guide SERDES PHY IP development from concept to customer-ready products.

You will oversee a diverse engineering team, collaborating across architecture, verification, physical implementation, and firmware to meet aggressive timing, power, and performance targets. We value deep expertise in Verilog/SystemVerilog, frontend design flows, and a proven record of mentoring top talent.

Qualifications

• Bachelor’s degree or higher in Electrical Engineering; 15+ years in complex technical development.
• Minimum 2 years’ experience in people management.
• Proficiency in Verilog and SystemVerilog design concepts.
• Strong front-end flows knowledge: linting, synthesis, STA, CDC/RDC, DFT, and power optimization.
• Excellent communication; able to work independently and with cross-functional teams.
• Understanding PCIe and Ethernet is a plus.

Responsibilities

• Lead a diverse design engineering team for next-generation SERDES PHY IP.
• Collaborate with architects, verification, physical implementation, and firmware teams.
• Plan and drive all phases of SERDES PHY IP design from spec to productization and support.
• Ensure timing, performance, and power goals across multiple design cycles.
• Mentor and develop team members, fostering innovation.
• Engage customers for successful IP integration into SoCs and address challenges.

Skills

Verilog / SystemVerilog

Front-end flows

People management

Mentoring

Leadership

PCIe / Ethernet knowledge

Education

Bachelor’s degree in Electrical Engineering

Tools

EDA tools

Job description

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a visionary technical leader with an unyielding passion for innovation in semiconductor design. With a foundation in electrical engineering anda track recordof managing high-performing design teams, you excel in guiding complex digital projects from concept to commercialization. Yourexpertisespans synthesizable VerilogandSystem Verilog, andyou’readept at navigating the intricacies of front-end flows, including linting, synthesis, static timing analysis, and power optimization. You thrive in collaborative environments, working seamlessly with cross-functional teams—architecture, verification, physical implementation, and firmware—to deliver industry-leadingSERDESPHY IP solutions.

What You’ll Be Doing:

• Leading a diverse team of design engineering the development of next-generation SERDES PHY IP solutions.
• Collaborating with architects, verification, physical implementation, and firmware teams to deliver comprehensive IP products.
• Planning,scheduling and driving all phases of SERDES PHY IP design, from specification through productization and customer support.
• Ensuring project success by achieving optimal timing, performance, and power goals across multiple design cycles.
• Mentoring and developing team members, fostering technical growth, and a culture of innovation.
• Engaging customers, providing support for successful IP integration into their SoCs, and addressing technical challenges.

The Impact You Will Have:

• Delivering industry-leading SERDES PHY IP solutions that set new benchmarks for speed, bandwidth, and efficiency.
• Empowering semiconductor customers to build high-performance, low-power chips for cutting-edge applications.
• Driving technical innovation that strengthens Synopsys’ leadership in the mixed-signal IP market.
• Mentoring and growing a world-class engineering team, ensuring continued excellence and market relevance.
• Enhancing product quality and reliability through rigorous design and verification processes/Flows.
• Facilitating successful customer adoption and satisfaction through expert support and problem-solving.

What You’ll Need:

• Bachelor’s degree or higher in Electrical Engineering, with 15 +years of complex technical development experience.
• Minimum 2 years’ experience in people management and employee development.
• Proficiency in modeling, synthesizableVerilogandSystem Verilogdesign concepts and implementation.
• Strong background in front-end design flows: Linting, synthesis, static timing analysis (STA),CDC/RDC, DFT, and power optimization.
• Excellent communication skills and the ability to work independently and collaboratively.
• Understanding the PCIe and Ethernet standard is a plus.

Who You Are:

• Self-starter independent leader who thrives in a fast-paced, innovative setting and can drive task still closure.
• Strong problem-solver with a strategic, analytical mindset.
• Inspirational leader who motivates and develops technical talent.
• Collaborative teamplayers whoexcelsin cross-functional environments.
• Effective communicator who can translate complex technical concepts to diverse audiences.

The Team You’ll Be A Part Of:

You’lljoin the SynopsysSERDESPHY IP team—a global, diverse group at the forefront of silicon IP innovation. Our team develops both digital and analog components, creating high-performance, high-bandwidth, low-latency, and low-power solutions for the world’s most advanced semiconductor technologies. We collaborate across engineering disciplines to deliver market-leading products and drive Synopsys’ leadership in chip design.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. #LI-NK4