Principal Engineer: RTL/STA Lead for High-Speed ICs

Microchip Technology Inc.; Saskatoon; On-site; CAD 150,000 - 210,000; Full time

Job summary

Microchip Technology Inc. is seeking a Principal Engineer to join the Communications Business Unit (CBU) Product Development team. You will lead the digital design, DFT, physical implementation, and STA signoff of ICs at block and top levels, using Cadence and Synopsys tools.

You will collaborate with RTL and DFT engineers, drive RTL-to-pre-layout netlist generation, and own STA across multiple macros, subsystems, and full-chip designs on advanced nodes.

Qualifications

• Bachelor’s or Graduate Degree in Computer Sciences, Electrical/Electronics/VLSI Engineering.
• 10 years of experience in synthesis, STA and Formal Verification with mainstream tools.
• Strong coding and scripting skills (TCL, Perl or Python).
• Hands-on experience with RTL Design, synthesis, low-power logic insertion using UPF/CPF and STA signoff of Macro’s and SoC Level.
• Good understanding of timing models, DFT, libs, hierarchical budgeting flows.
• Tapeout experience of 1 or more projects with 16nm or smaller silicon process technologies.
• Hands-on experience with synthesis tools like Cadence Genus OR Synopsys-DC/FC.
• Good verbal and written communication skills in English, strong interpersonal skills.

Responsibilities

• Develop macro constraints (Synthesis, STA & Layout), ram generations, flow configuration for High-speed complex macros and Subsystems.
• STA sign off for all levels of design hierarchy for multiple modes and multiple corners (MMMC).
• Develop/understand flow and methodology for RTL Synthesis.
• Ability to pick up new flows, learn on the job and influence QOR is a must.
• Co-work with RTL and DFT engineers and interact with project teams to ensure the right constraints/deliverables are in place.
• Ensure the Quality of deliverables pre/post netlists (CLP, LEC, In-house tool checks)
• Close interactions with APR team to ensure that floorplanning/macro placements/quality of deliverables are in the right direction.

Skills

Analytical and debugging skills

Coding & scripting

English communication

Education

Bachelor’s or Graduate Degree in Computer Sciences, Electrical/Electronics/VLSI Engineering

Tools

Cadence Genus

Synopsys-DC/FC

UPF/CPF

Job description

Microchip Technology Inc. is seeking a Principal Engineer to join the Communications Business Unit (CBU) Product Development team. You will lead the digital design, DFT, physical implementation, and STA signoff of ICs at block and top levels, using Cadence and Synopsys tools.

You will collaborate with RTL and DFT engineers, drive RTL-to-pre-layout netlist generation, and own STA across multiple macros, subsystems, and full-chip designs on advanced nodes.