Principal RTL Design Engineer

Microchip Technology Inc.

Burnaby

On-site

CAD 120,973 - 261,640

Full time

14 days+

Get more replies from employers

Send a job-specific resume in minutes.

Benefits offered by this job

Health benefits starting day one
Retirement savings plans
Employee stock program

Job summary

Microchip Technology Inc. in Burnaby, BC is seeking engineers to contribute to the mixed-signal/ASIC development lifecycle. You will work on RTL design, verification, and SSD/DDR/Flash PHY subsystems, collaborating with architects, verification, firmware, and backend teams.

The role emphasizes hands-on design, debugging, and documentation across the ASIC flow, with opportunities to advance in a global technology leader.

Qualifications

  • Bachelor’s/Master’s/PhD in Electrical/Computer Engineering or related field.
  • 2–10 years of ASIC development experience (level dependent).
  • Strong RTL design/verification using Verilog, SystemVerilog, or VHDL.
  • Hands-on debugging experience with lab equipment (oscilloscopes, logic analyzers).
  • Experience with C/C++ and scripting (Python, Perl, TCL, Shell).
  • Knowledge of DDR and Flash Controller/PHY is a plus.

Responsibilities

  • Participate in full ASIC design cycle from design to silicon bring-up and debugging.
  • Design RTL using Verilog/SystemVerilog; integrate IP blocks and supporting logic.
  • Run CDC analysis, lint checks, and power simulations.
  • Collaborate with verification teams; contribute to verification plans and debugging.
  • Support STA timing closure with backend team; analyze timing paths.
  • Develop test plans, configurations, and provide debug support with Product Eng.
  • Develop C-based drivers for DDR/Flash PHY and validate via simulations.
  • Produce high-quality design/verification/test documentation.

Skills

RTL design
Verilog/SystemVerilog
VHDL
ASIC verification
C/C++
Scripting (Python, Perl, TCL, Shell)
Lab debugging equipment

Education

Electrical/Computer Engineering degree

Tools

Oscilloscopes
Logic analyzers
RTL design CAD tools

Job description

Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc.


People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence.


Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.


Visit our careers page to see what exciting opportunities and company perks await!


Job Description

The Mixed Signal Development Group is responsible for delivering high performance analog, digital and mixed-signal IP to various divisions within Microchip. Leveraging advanced CMOS processes, the team develops mixed-signal integrated circuits for wireline applications. From DDR to flash controller and PHY subsystems, our work enables seamless connectivity between Microchip products and the external world.


As a member of the Mixed-Signal Development Group, you will be working closely with architects, other digital design engineers, verification engineers, firmware engineers, and cross-functional teams. You will contribute to the RTL design and verification of DDR or flash controller/PHY subsystem blocks, playing a key role throughout the ASIC development lifecycle.


Responsibilities


  • Participate in the full ASIC design cycle, including design, verification, backend implementation, silicon bringup and debugging.

  • Design RTL using Verilog/SystemVerilog, integrate IP blocks, and implement supporting logic (e.g., clock/reset, Jtag, DFT, SRAMs, etc)

  • Run clock domain crossing (CDC) analysis, lint check and power simulations.

  • Work closely with verification teams or involve in some verification, review, optimize, and execute verification plans; debug design and simulation issues

  • Work closely with backend team on STA timing closure, help analyze timing critical paths and resolve STA timing issues; Run trial synthesis to estimate logic depth and area early in the design cycle

  • Work closely with Product Engineering team on characterization planning and execution as well as DFT related tasks, create test plans, test configuration, and provide debug support

  • Develop C-based drivers for DDR/Flash PHY, perform simulation-based validation, and support silicon bring-up in the lab

  • Produce high-quality design, verification, and test documentation


Requirements/Qualifications


  • Bachelor’s/Master’s/PhD in Electrical Engineering, Computer Engineering/Science, or related field

  • 2–10 years of ASIC development experience (level dependent)

  • Strong experience in RTL design and verification using Verilog, SystemVerilog, or VHDL

  • Hands-on debugging experience with lab equipment (e.g., oscilloscopes, logic analyzers)

  • Experience or Knowledge in C/C++ and scripting/automation (Python, Perl, TCL, Shell)

  • Working knowledge of DDR and Flash Controller/PHY/memory considered an asset

  • Strong problem-solving skills with the ability to work independently and proactively

  • Ability to collaborate effectively in a team-oriented environment


Travel Time

0% - 25%


Pay Range

We offer a total compensation package that ranks among the best in the industry. It consists of competitive base pay, restricted stock units, and quarterly bonus payments. In addition to these components, our package includes health benefits that begin day one, retirement savings plans, and an industry leading IESPP program with a 6-month look back feature. Find more information about all our benefits at the link below:


Benefits of working at Microchip

The annual base salary range for this position is $86,000-$186,000.*



  • Range is dependent on numerous factors including job location, skills and experience.


To all recruitment agencies: Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.

Get your free, confidential resume review.
or drag and drop your file here.
Similar jobs

Similar jobs worth comparing

Technical Staff Engineer - Design
Technical Staff Engineer - Design

FHLB Des Moines • Burnaby

On-site
CAD 149,000 - 314,000
Health benefits that begin day one
Retirement savings plans
Restricted stock units
+1
Technical Staff Engineer - Design
Technical Staff Engineer - Design

Microchip Technology Inc. • Burnaby

On-site
CAD 107,000 - 226,000
Health benefits from day one
Retirement savings plan
Employee stock purchase plan (ESPP)
Principal Engineer-Firmware
Principal Engineer-Firmware

Microchip Technology Inc. • Burnaby

On-site
CAD 86,000 - 186,000
Health benefits from day one
Retirement savings plans
IESPP program with 6-month look back
Technical Staff Engineer - Emulation
Technical Staff Engineer - Emulation

Microchip Technology Inc. • Burnaby

On-site
CAD 148,000 - 314,000
Health benefits from day one
Retirement savings plans
IESPP program with 6-month look back
Principal Engineer-Applications
Principal Engineer-Applications

Microchip Technology Inc. • Burnaby

On-site
CAD 120,000 - 261,000
Health benefits starting day one
Retirement savings plans
Quarterly bonus payments
Senior Technical Staff Engineer - Analog Design
Senior Technical Staff Engineer - Analog Design

Microchip Technology Inc. • Ottawa

On-site
CAD 209,000 - 279,000
Health benefits from day one
Retirement savings plans
Quarterly bonus
+2
Principal Enginer – Firmware
Principal Enginer – Firmware

FHLB Des Moines • Ottawa

Hybrid
CAD 107,000 - 157,000
Restricted stock units
Quarterly bonus payments
Health benefits from day one
+2
Principal Engineer-Firmware
Principal Engineer-Firmware

FHLB Des Moines • Burnaby

On-site
CAD 86,000 - 186,000
Health benefits from day one
Quarterly bonus payments
Restricted stock units (RSUs)
Principal DSP Firmware Engineer
Principal DSP Firmware Engineer

Microchip Technology • Ottawa

On-site
CAD 120,000 - 180,000
Health benefits from day one
Restricted stock units
Quarterly bonus payments
+2
Principal DSP Firmware Engineer
Principal DSP Firmware Engineer

Microchip Technology Inc. • Ottawa

On-site
CAD 149,000 - 219,000
Health benefits from day one
Restricted stock units (RSUs)
Quarterly bonus payments
+2